Abstract: A method may include at least partially initializing a trellis of an SE engine at least partially based on predetermined state information about a communication channel associated with an incoming data stream; and processing, via the MLSE engine, the incoming data stream to further initialize the trellis and decode the incoming data stream.

Abstract: A method may include: initializing four states of a trellis, the four states corresponding to the four possible symbol levels in PAM4, where a respective initial state starts with an initial score and an empty survivor path; for respective possible transitions between the four initial states and four possible current states of the trellis, determining expected PAM4 symbols; determining error associated with respective transitions based on differences between a received PAM4 symbol and the expected PAM4 symbols; discarding transitions where the error indicates a difference greater than a single signal level, and keep the other transitions; and for respective current state groups of a two state trellis, determining one of the incoming transitions that was not discarded having the highest likelihood of being associated with a transmitted symbol.

Abstract: A method may include generating a first computational circuit of a current iteration of a Berlekamp algorithm, the first computational circuit to determine a Berlekamp discrepancy value at least partially based on a current Error-Locator Polynomial (ELP) and observed syndromes; and generating a second computational circuit of the current iteration of the Berlekamp algorithm, the second computational circuit to determine an intermediate value, the intermediate value useable by one or more first computational circuits of one or more subsequent iterations of the Berlekamp algorithm to determine Berlekamp discrepancy values.

Abstract: A method may include generating a status signal, the status signal to indicate a status of Error-Locator-Polynomial (ELP) determination by an ELP determination circuit; and controlling the ELP determination by the ELP determination circuit at least partially responsive to a value of the status signal.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: A method and system are provided for error correction. After row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) may be concurrently created, for each of a plurality of modified column codewords (CCW?), by multiplying initial calculated parity P by a generator matrix G. Each CCW? may include an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW? is present in the ACD portion for one of the other CCW?. In contrast to known approaches, the method and system may provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords, each bit in the modified parity in one modified codeword is present in another codeword.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.

Abstract: A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.

Abstract: A method and system are provided for error correction. In an implementation, after row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) are concurrently created, for each of a plurality of modified column codewords (CCW), by multiplying initial calculated parity P by a generator matrix G. In an example implementation, each CCW? includes an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW is present in the ACD portion for one of the other CCW?. In contrast to known approaches, in an implementation the method and system described herein provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords generated according to the method and system described herein, each bit in the modified parity in one modified codeword is present in another codeword.

Abstract: A forward error correction decoder and method of decoding a codeword is provided. The decoder comprises a convergence processor for estimating an expectation of codeword convergence. The convergence processor is configured to calculate a first value of a figure of merit; calculate a second value of the figure of merit; combine the second value of the figure of merit and the first value of the figure of merit to produce a progress value; compare the progress value of the decoding to a progress threshold; and increase a maximum number of iterations of the decoder if the progress value is greater than the progress threshold. The maximum number of iterations may be initially set to a low number beneficial for power consumption and raw throughput. Increasing the maximum number of iterations devotes additional resources to a particular codeword and is beneficial for error rate performance.

Abstract: A method and apparatus for a quasi-cyclic low density parity check (QC-LDPC) decoder utilizes a parity check matrix (H matrix) having a matrix value for each row and column position in the matrix. Each matrix value is associated with an initial soft information element where, for each one of the matrix values associated with a constrained row, the one of the matrix values is constrained to a set of constraint values associated with a set of initial soft information elements. The set of initial soft information elements excludes a number of soft information elements that immediately precede a first initial soft information element. The first initial soft information element is associated with a selected first matrix value associated with a first row that immediately precedes the constrained row, and with the same column as the one of the matrix values in the constrained row.

Abstract: A method for boost floor mitigation during a decoding operation performed by a decoder is disclosed herein. The method includes: monitoring for a floor error condition while performing the decoding operation; if a floor error condition has been detected, then: clearing a feedback delay memory in the decoder; downscaling main memory values in the decoder; applying a gain in low-rank columns; and continuing to perform the decoding operation.

Abstract: A method and apparatus as described herein provide a novel modification to any iterative FEC decoder method that can improve FER performance in the error floor region. Many iterative FEC methods, such as commonly used LDPC decoders, have error floors where the performance of the decoder does not improve below a certain threshold. Error Floors are caused by trapping sets from which traditional methods cannot escape. With Stochastic Floor Mitigation, according to embodiments of the present disclosure, noise is strategically added to the operations occurring during decoding resulting in significantly improved error floor performance.

Abstract: An FEC codeword comprises channel information indicating the reliability of the information contained by the FEC codeword. The channel information can be used to generate an initial error channel estimate. Based on the initial error channel estimate, an FEC decoder can decode the FEC codeword to increase the reliability of the information contained by the FEC codeword. According to the present disclosure, a method and system of decoding comprises: comparing a current codeword to a previous codeword in order to identify bits corrected between the previous and current codewords; revising an error channel estimate based on the identified corrected bits, the revised estimate representing a change in the error channel over time; and decoding the codeword based on the revised error channel estimate.

Abstract: Methods and apparatus are described for determining, via a Hybrid Automatic Repeat Request (HARQ) module, that a maximum number of retransmissions has been reached for a HARQ packet. The HARQ module may communicate an internal NACK to a message retransmission module indicating a transmission failure. The message retransmission module may retransmit at least a part of the message. The retransmission may be performed prior to the expiration of a timer.

Abstract: Forward error correction (FEC) decoders, such as Low Density Parity Check (LDPC) decoders are described. Described FEC decoders minimize the number of internal bits in a layered processor of an LDPC decoder while maintaining high coding gain operation of the LDPC decoder. Minimizing the number of internal bits in a layered processor is achieved by non-linearly companding the soft information into lower precision format while maintaining the dynamic range of the data bits. Described FEC decoders may generate updated soft information having a precision that is equal to the channel precision.

Abstract: A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.