Abstract: A system and method for an improved method of decoding a pulse amplitude modulation (PAM) symbol group employing a convolutional coding trellis are disclosed. The method may include receiving a first symbol group from a transmitter at a first time and identifying a first path and a second path corresponding to a state of the transmitter at the first time and containing at least two symbols. The method may include storing a final symbol of the first path and a final symbol of the second path. The method may include receiving a second symbol group at a second time and identifying, based on the final symbol of the first path, a third path corresponding to a state of the transmitter at the second time and identifying, based on the final symbol of the second path, a fourth path corresponding to the state of the transmitter at the second time.

Abstract: A system and method for providing additional sideband signaling using PAM5 convolution code modulation are disclosed. The method may include selecting a transition group pattern. The method may also include pulling a first sideband signaling bit on a first in, first out basis. The method may additionally include appending the first sideband signaling bit to the selected transition group pattern. The method may further include transmitting a first data stream containing the selected transition group pattern and the first sideband signaling bit.

Abstract: An apparatus and method are disclosed for error correction in Reed-Solomon (RS) code decoders. The apparatus may include a receiver configured to receive flow control unit (FLIT) blocks from a transmitter, wherein the FLIT blocks are encoded using Reed-Solomon codes with predefined burst error characteristics for transmission across one or more lanes. A FLIT block processing unit organizes and processes the FLIT blocks for decoding. An error locator polynomial computation module identifies error locations by generating an error locator polynomial based on the FLIT blocks, determining a symmetrical error pattern from the predefined burst error characteristics, defining a constrained polynomial root search space based on the symmetrical error pattern, and determining roots of the error locator polynomial within the constrained search space to identify error locations.

Abstract: Disclosed herein are apparatus, system, method, and computer-readable medium aspects for error correction in a PCI Express (PCIe) Forward Error Correction (FEC) system. An example method may include receiving an FEC block comprising interleaved Reed-Solomon (RS) codewords, decoding the FEC block using a standard decoder to correct up to three successive RS symbol errors, and if the standard decoder fails, attempting error correction using one or more parallel decoders, comprising at least a 4-burst decoder to correct a single burst error spanning four RS symbols. The method may include selecting a corrected FEC block from an output of one of the standard decoder and the one or more parallel decoders based on successful error correction. The one or more parallel decoders can further comprise a 5-burst decoder and a 6-burst decoder.

Abstract: A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer/deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

Abstract: A method may include receiving a plurality of input bits; determining, using a convolutional trellis, a state transition of the convolutional trellis at least partially responsive to a first subset of the input bits; selecting, from a symbol alphabet that is a subset of a constellation of signal?level patterns of a multi-level modulation scheme, a group of symbols pre?associated with the determined state transition and identified at least partially by a second subset of the input bits; and serializing and transmitting the selected group of symbols.

Abstract: Described is a compound for substituting amino acids of proteins or peptides, wherein the compound has the formula (1) wherein the stereocenter C1* represents CH that either results in the D- or L-form of the compound of formula (1); A? is a negatively charged ion compensating the positive charge; X1 is H or an amine protecting group; X2 is OH, an ester residue or an amide residue or an activated carboxylic acid derivate to be used for the formation of an amide bond; Y1, Y2 and Y3 are independently from each other a C1-C6 alkyl, and Z1 and Z2 are independently from each other a nucleobase, a C1 to C16 alkyl group, an aromatic residue or a heteroaromatic residue, wherein the aromatic residue or the heteroaromatic residue contains one 5, 6, or 7-membered ring or two condensed 5, 6, or 7-membered rings sharing two carbon atoms, wherein the aromatic residue or the heteroaromatic residue can be substituted by a linear or branched C1 to C16 alkyl group and/or a further aromatic group.

Abstract: A method may include receiving eight bits of information; determining a state transition of a convolutional trellis at least partially based on a two-bit portion of the eight bits of information; determining a group of PAM-modulated symbols at least partially based on the determined state transition of the convolutional trellis, the eight bits of information, and a set of predetermined groups of PAM-modulated symbols pre-associated with the determined state transition of the convolutional trellis; and encoding the eight bits of information into the determined group of PAM-modulated symbols.

Abstract: A method may include at least partially initializing a trellis of an SE engine at least partially based on predetermined state information about a communication channel associated with an incoming data stream; and processing, via the MLSE engine, the incoming data stream to further initialize the trellis and decode the incoming data stream.

Abstract: A method may include: initializing four states of a trellis, the four states corresponding to the four possible symbol levels in PAM4, where a respective initial state starts with an initial score and an empty survivor path; for respective possible transitions between the four initial states and four possible current states of the trellis, determining expected PAM4 symbols; determining error associated with respective transitions based on differences between a received PAM4 symbol and the expected PAM4 symbols; discarding transitions where the error indicates a difference greater than a single signal level, and keep the other transitions; and for respective current state groups of a two state trellis, determining one of the incoming transitions that was not discarded having the highest likelihood of being associated with a transmitted symbol.

Abstract: A method may include generating a first computational circuit of a current iteration of a Berlekamp algorithm, the first computational circuit to determine a Berlekamp discrepancy value at least partially based on a current Error-Locator Polynomial (ELP) and observed syndromes; and generating a second computational circuit of the current iteration of the Berlekamp algorithm, the second computational circuit to determine an intermediate value, the intermediate value useable by one or more first computational circuits of one or more subsequent iterations of the Berlekamp algorithm to determine Berlekamp discrepancy values.

Abstract: A method may include generating a status signal, the status signal to indicate a status of Error-Locator-Polynomial (ELP) determination by an ELP determination circuit; and controlling the ELP determination by the ELP determination circuit at least partially responsive to a value of the status signal.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: A method and system are provided for error correction. After row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) may be concurrently created, for each of a plurality of modified column codewords (CCW?), by multiplying initial calculated parity P by a generator matrix G. Each CCW? may include an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW? is present in the ACD portion for one of the other CCW?. In contrast to known approaches, the method and system may provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords, each bit in the modified parity in one modified codeword is present in another codeword.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.

Abstract: A method and system are provided for drift compensation, providing a live data approach to sampler offset calibration, such as for voltage and/or temperature (VT) drift. A serializer/deserializer (SerDes) system includes a SerDes receiver and receiver logic, the receiver logic including a forward error correction (FEC) module. A drift compensation device, or drift compensation engine, receives live error corrections from the FEC module based on FEC operations performed on live traffic passing through the SerDes receiver. A drift compensation command is provided to a data sampler in the SerDes receiver, to adjust a sampling voltage of the data sampler. When the system includes a plurality of data samplers, the drift compensation device determines the data sampler with which an error correction is associated. The drift compensation command can be sent after a threshold criterion is satisfied, such as completion of a statistics collection period, or a threshold number of corrections.

Abstract: A method and system are provided for error correction. In an implementation, after row encoding and column encoding, additional codeword data (ACD) and modified parity (P?) are concurrently created, for each of a plurality of modified column codewords (CCW), by multiplying initial calculated parity P by a generator matrix G. In an example implementation, each CCW? includes an ACD portion and a P? portion such that each bit in the P? portion of a selected CCW is present in the ACD portion for one of the other CCW?. In contrast to known approaches, in an implementation the method and system described herein provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords generated according to the method and system described herein, each bit in the modified parity in one modified codeword is present in another codeword.