Abstract: A method and decoder are provided to decode a Low Density Parity Check codeword. An additional check processor performs hard-decision processing functions on the LDPC codeword in order to avoid running unnecessary decoder iterations. The method comprises: receiving the ECC codeword at a memory, the received ECC codeword comprising ECC data bits, ECC parity bits, and error detection code bits; soft-decision decoding the received ECC codeword at a soft-decision decoder, to update the ECC codeword according to ECC parity check equations; hard-decision processing the received ECC codeword at a check processor, while the soft-decision decoder performs the soft-decision decoding, to verify the ECC data bits using the error detection code bits; terminating the soft-decision decoding when the ECC data bits are verified, regardless of whether the updated ECC codeword satisfies all of the ECC parity check equations; and, outputting the decoded ECC codeword from the memory after termination of the decoding.

Abstract: A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: A method of decoding a primary codeword and a set of secondary codewords stored in a non-volatile memory (NVM), which includes reading, from the NVM, the primary codeword and all the secondary codewords and storing them in a second memory. The primary codeword is then read from the second memory and decoded, utilizing a soft-decision decoder, based on a log-likelihood ratio (LLR) vector. When the decoding of the primary codeword is unsuccessful: each secondary codeword of the set of secondary codewords is read from the second memory and decoded, utilizing a hard-decision decoder, to identify and correct errored data bits in the each secondary codeword and to determine a location of each errored data bit in the primary codeword. An adjusted LLR vector is generated by adjusting the LLR for each primary codeword data bit based on the determined locations of the errored data bits in the primary codeword.

Abstract: A system and method of decoding a Reed-Solomon code using a Reed-Solomon decoder comprising an erasure location selector, multiple syndrome formers and multiple Berlekamp-Massey decoders that share a single error correction unit, and means for selecting a Berlekamp-Massey decoder output as the input to the error correction unit. The method improves the bit error rate performance of the Reed-Solomon decoder compared to known hard-decision and soft-decision Reed-Solomon decoders. The Reed-Solomon decoder also provides hardware area and power savings over more complex Reed-Solomon decoders.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.

Abstract: Methods and apparatus are described for determining, via a Hybrid Automatic Repeat Request (HARQ) module, that a maximum number of retransmissions has been reached for a HARQ packet. The HARQ module may communicate an internal NACK to a message retransmission module indicating a transmission failure. The message retransmission module may retransmit at least a part of the message. The retransmission may be performed prior to the expiration of a timer.

Abstract: A circuit for reducing phase errors in a digital communication systems signal is provided. The circuit comprises a demodulator block, a feed-forward path, a feed-back path, and a slicer. The demodulator block generates a plurality of samples from the signal and determines for each sample a corresponding phase error. The feed-forward path is configured to reduce in the signal a high frequency component of the phase errors. The feed-back path configured to reduce in the signal a low frequency component of the phase errors. The slicer selectively forwards phase errors to the feed-forward path or the feed-back path based on a respective magnitude of the phase error when operating in a decision-directed mode.

Abstract: Methods and apparatus are described for determining, via a Hybrid Automatic Repeat Request (HARQ) module, that a maximum number of retransmissions has been reached for a HARQ packet. The HARQ module may communicate an internal NACK to a message retransmission module indicating a transmission failure. The message retransmission module may retransmit at least a part of the message. The retransmission may be performed prior to the expiration of a timer.

Abstract: Methods and apparatus are described for determining, via a Hybrid Automatic Repeat Request (HARQ) module, that a maximum number of retransmissions has been reached for a HARQ packet. The HARQ module may communicate an internal NACK to a message retransmission module indicating a transmission failure. The message retransmission module may retransmit at least a part of the message. The retransmission may be performed prior to the expiration of a timer.

Abstract: Methods and apparatus are described for determining, via a Hybrid Automatic Repeat Request (HARQ) module, that a maximum number of retransmissions has been reached for a HARQ packet. The HARQ module may communicate an internal NACK to a message retransmission module indicating a transmission failure. The message retransmission module may retransmit at least a part of the message. The retransmission may be performed prior to the expiration of a timer.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: A mechanism is provided to allow an HARQ retransmission to more closely match the receiver's need for energy with the additional energy sent over the wireless link. In one aspect, the receiver sends the transmitter qualitative feedback which indicates to the transmitter an approximate amount of additional energy that the receiver needs to successfully decode the transmission.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: A mechanism is provided to allow an HARQ retransmission to more closely match the receiver's need for energy with the additional energy sent over the wireless link. In one aspect, the receiver sends the transmitter qualitative feedback which indicates to the transmitter an approximate amount of additional energy that the receiver needs to successfully decode the transmission.

Abstract: An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency.

Abstract: An FFT processor using a single delay path and a permuter provides a reduction in the implementation area and a related reduction in power consumption through efficiencies obtained by the modification of a butterfly unit and the use of a novel interleaver. The modified butterfly unit is obtained by removal of complex variable multipliers, which is possible due to the simplification of twiddle factors in the stages that correspond to the modified butterfly unit.