Abstract: Data are frequently transmitted via a dual bus line by means of differential signals which are evaluated by a differential amplifier, particularly for reasons of protection against interference. However, such a differential amplifier only has a limited input voltage range, or a dead voltage range of the input signals within which it is not capable of operating. To prevent the voltages on both bus lines from getting into this dead voltage range, either due to a common-mode interference signal on the bus lines or due to a voltage dip in the feed voltage of the differential amplifier, the two bus lines are connected in accordance with the invention to an adjusting circuit which changes the voltages of both bus lines by the same amount in the direction out of the dead voltage range. This prevents unspecified conditions of the differential amplifier without significantly influencing the differential signal on the two bus lines. The application for an integrated memory is described.

Abstract: A push-pull output circuit which is powered by a 5-V supply voltage and in which the "push" part comprises a PMOS transistor and the "pull" comprises a PMOS transistor and an NMOS transistor. The NMOS transistor is driven via a detection circuit so that no hot carrier stress occurs in the NMOS transistor.

Abstract: A memory has input buffer circuit which provides high immunity to problems associated with address float while providing high speed for both decoder selection and for transition detection. The input buffer circuit includes a pair of input NOR gates which provides for independent signal paths to a cross-coupled latch. Independent hysteresis circuits are provided to each signal path between the two NOR gates and the cross-coupled latch. This allows for independently selecting the amount of dc margin and hysteresis so that the use of hysteresis does not adversely effect dc margin.

Abstract: A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.