Patents by Inventor Peter Hughes
Peter Hughes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240168460Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for computer aided design of physical structures include, in at least one aspect, a fully automatic method of converting a generative design into an editable, watertight B-Rep by leveraging the generative solver input and representation to: (1) embed the exact input solid boundary surfaces where the design coincides with the input, (2) approximate everywhere else the design boundary with globally smooth, editable “organic” surfaces, and (3) join all surfaces to form a generative design output B-Rep.Type: ApplicationFiled: December 12, 2023Publication date: May 23, 2024Inventors: Martin Cvetanov Marinov, Peter Hugh Charrot, Suguru Furuta, Nandakumar Santhanam, Justin Nicholas Hallet, Stephen Alan Barley, Jean Alison Flower, Gordon Thomas Finnigan, Siavash Navadeh Meshkat, Iain Edward Henley, Tristan Ward Barback, Maciej Sapun, Marco Amagliani, Pawel Wolski
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Patent number: 11921491Abstract: Methods, systems, and apparatus for computer aided design of physical structures include: producing a quad parameterization computer model (including quad parameter domains) of a polygon mesh, where quad parameter domain(s) adjacent to a boundary curve interpolate the boundary curve; and forming a computer model of a three dimensional object by constructing locally refinable surface representation(s) from the quad parameterization computer model, refining a boundary of the locally refinable surface representation(s) to approximate the boundary curve within a first tolerance value set in accordance with a smallest dimension representable by a geometry modeling kernel, freezing control points of the locally refinable surface representation(s) at the boundary, and modifying remaining interior portions of the locally refinable surface representation(s) to approximate the polygon mesh within a second tolerance value that is at least an order of magnitude larger than the first tolerance value.Type: GrantFiled: May 12, 2021Date of Patent: March 5, 2024Assignee: Autodesk, Inc.Inventors: Martin Cvetanov Marinov, Marco Amagliani, Peter Hugh Charrot
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Patent number: 11886165Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for computer aided design of physical structures include, in at least one aspect, a fully automatic method of converting a generative design into an editable, watertight B-Rep by leveraging the generative solver input and representation to: (1) embed the exact input solid boundary surfaces where the design coincides with the input, (2) approximate everywhere else the design boundary with globally smooth, editable “organic” surfaces, and (3) join all surfaces to form a generative design output B-Rep.Type: GrantFiled: April 13, 2021Date of Patent: January 30, 2024Assignee: Autodesk, Inc.Inventors: Martin Cvetanov Marinov, Peter Hugh Charrot, Suguru Furuta, Nandakumar Santhanam, Justin Nicholas Hallet, Stephen Alan Barley, Jean Alison Flower, Gordon Thomas Finnigan, Siavash Navadeh Meshkat, Iain Edward Henley, Tristan Ward Barback, Maciej Sapun, Marco Amagliani, Pawel Wolski
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Publication number: 20230137983Abstract: Forming a hardmask layer for reactive ion etching includes depositing a hardmask above an underlayer. The hardmask includes a layer of magnesium oxide having a thickness of up to 10 nm. A resist layer is deposited above the hardmask and developed to form a pattern that exposes portions of the hardmask. The pattern is transferred from the resist layer to the hardmask by rinsing exposed portions of the hardmask with a deionized water solution.Type: ApplicationFiled: October 28, 2021Publication date: May 4, 2023Inventors: Aakash Pushp, M A Mueed, Benjamin Madon, Noel Arellano, Krystelle Lionti, Gregory Michael Wallraff, Anthony Bock Fong, Brian Peter Hughes, Vincent Ouazan-Reboul
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Patent number: 11621200Abstract: This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.Type: GrantFiled: May 31, 2022Date of Patent: April 4, 2023Assignee: Diodes IncorporatedInventor: Peter Hugh Blair
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Publication number: 20220336445Abstract: This application provides a process for making a circuit of a bipolar junction transistor (BJT). The switchable short in one implementation of the invention is formed in a semiconductor wafer. A collector region is formed in the semiconductor wafer and inside of the collector region, a first base region is formed. An emitter region is formed inside the base region to form the BJT. A drain region is also formed inside the base region adjacent to the emitter region. A gate is formed over a portion of the base region adjacent to the drain region and the emitter region. The gate is connected to the collection region.Type: ApplicationFiled: May 31, 2022Publication date: October 20, 2022Applicant: Diodes IncorporatedInventor: Peter Hugh Blair
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Patent number: 11393811Abstract: The invention solves the problem of depressed SOA of a bipolar junction transistor (BJT) when operated in an open base configuration by integrating in the same semiconductor chip a switchable short between the base and the emitter of the BJT. The switchable short switches between a high resistive value when the collector voltage of the BJT is lower than the base voltage. and a lower resistive value when the collector voltage is higher than the voltage base to effectively lower the BJT current gain (hFE). The switchable short in one implementation of the invention is in the form of a MOSFET with its gate connected to the BJT collector. The invention further teaches disposing in the integrated circuit chip a junction diode with a breakdown voltage lower than the BVCBO of the BJT. The addition of the junction diode provides a measure of maintaining the effectiveness of the MOSFET as switchable short at a reduced size.Type: GrantFiled: August 2, 2021Date of Patent: July 19, 2022Assignee: Diodes IncorporatedInventor: Peter Hugh Blair
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Patent number: 11363083Abstract: Methods and apparatus are disclosed for managing streamed audio communication sessions between user devices (50) configured to send streamed data indicative of received audio contributions from respective participants in a multiple-participant audio communication session via a communications network to one or more other user devices (50) for conversion to audio representations of said received audio contributions for other participants.Type: GrantFiled: December 21, 2018Date of Patent: June 14, 2022Assignee: BRITISH TELECOMMUNICATIONS public limited companyInventors: Ian Kegel, Karis Bailey, Martin Reed, Peter Hughes
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Publication number: 20220037311Abstract: The invention solves the problem of depressed SOA of a bipolar junction transistor (BJT) when operated in an open base configuration by integrating in the same semiconductor chip a switchable short between the base and the emitter of the BJT. The switchable short switches between a high resistive value when the collector voltage of the BJT is lower than the base voltage. and a lower resistive value when the collector voltage is higher than the voltage base to effectively lower the BJT current gain (hFE). The switchable short in one implementation of the invention is in the form of a MOSFET with its gate connected to the BJT collector. The invention further teaches disposing in the integrated circuit chip a junction diode with a breakdown voltage lower than the BVCBO of the BJT. The addition of the junction diode provides a measure of maintaining the effectiveness of the MOSFET as switchable short at a reduced size.Type: ApplicationFiled: August 2, 2021Publication date: February 3, 2022Applicant: Diodes IncorporatedInventor: Peter Hugh Blair
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Publication number: 20210263499Abstract: Methods, systems, and apparatus for computer aided design of physical structures include: producing a quad parameterization computer model (including quad parameter domains) of a polygon mesh, where quad parameter domain(s) adjacent to a boundary curve interpolate the boundary curve; and forming a computer model of a three dimensional object by constructing locally refinable surface representation(s) from the quad parameterization computer model, refining a boundary of the locally refinable surface representation(s) to approximate the boundary curve within a first tolerance value set in accordance with a smallest dimension representable by a geometry modeling kernel, freezing control points of the locally refinable surface representation(s) at the boundary, and modifying remaining interior portions of the locally refinable surface representation(s) to approximate the polygon mesh within a second tolerance value that is at least an order of magnitude larger than the first tolerance value.Type: ApplicationFiled: May 12, 2021Publication date: August 26, 2021Inventors: Martin Cvetanov Marinov, Marco Amagliani, Peter Hugh Charrot
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Publication number: 20210232120Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for computer aided design of physical structures include, in at least one aspect, a fully automatic method of converting a generative design into an editable, watertight B-Rep by leveraging the generative solver input and representation to: (1) embed the exact input solid boundary surfaces where the design coincides with the input, (2) approximate everywhere else the design boundary with globally smooth, editable “organic” surfaces, and (3) join all surfaces to form a generative design output B-Rep.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Inventors: Martin Cvetanov Marinov, Peter Hugh Charrot, Suguru Furuta, Nandakumar Santhanam, Justin Nicholas Hallet, Stephen Alan Barley, Jean Alison Flower, Gordon Thomas Finnigan, Siavash Navadeh Meshkat, Iain Edward Henley, Tristan Ward Barback, Maciej Sapun, Marco Amagliani, Pawel Wolski
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Patent number: 11016470Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for computer aided design of physical structures include: obtaining a first 3D model including a polygon mesh associated with one or more modelled solids, the one or more modelled solids being in a boundary representation format; producing from the polygon mesh a quad patch network that combines, using transfinite interpolation, the polygon mesh with one or more smooth boundary curves corresponding to the one or more modelled solids; defining one or more locally refinable smooth surface representations using the quad patch network as input and based at least in part on a smallest dimension representable by a geometry modeling kernel of a computer aided design program; and combining the one or more locally refinable smooth surface representations with the one or more modelled solids to form a second 3D model that is watertight at the one or more smooth boundary curves.Type: GrantFiled: April 18, 2019Date of Patent: May 25, 2021Assignee: Autodesk, Inc.Inventors: Martin Cvetanov Marinov, Marco Amagliani, Peter Hugh Charrot
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Publication number: 20210043777Abstract: A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.Type: ApplicationFiled: October 28, 2020Publication date: February 11, 2021Applicant: Diodes IncorporatedInventors: Peter Hugh Blair, Lee Spencer Riley
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Patent number: 10854759Abstract: A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.Type: GrantFiled: April 1, 2016Date of Patent: December 1, 2020Assignee: Diodes IncorporatedInventors: Peter Hugh Blair, Lee Spencer Riley
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Patent number: 10666738Abstract: To represent the indirect lifecycle binding between the validity of data for a given topic, and the presence of sessions responsible for updating the data associated with that topic, sessions may register a policy referred to herein as a “session will” against specific nodes in the topic tree maintained by a data distribution system server. A session will binds the lifecycle of the topic node to that of the registering session. When a session that is responsible for updating a particular topic is disconnected, the data distribution system server initiates actions in accordance with the session will to determine how to manage updating the topic and the sub-topics in the topic path.Type: GrantFiled: October 17, 2016Date of Patent: May 26, 2020Assignee: Push Technology LimitedInventors: Philip Allan George Aston, Peter Hughes, Patrick Joseph Walsh
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Publication number: 20200150624Abstract: Methods, systems, and apparatus, including medium-encoded computer program products, for computer aided design of physical structures include: obtaining a first 3D model including a polygon mesh associated with one or more modelled solids, the one or more modelled solids being in a boundary representation format; producing from the polygon mesh a quad patch network that combines, using transfinite interpolation, the polygon mesh with one or more smooth boundary curves corresponding to the one or more modelled solids; defining one or more locally refinable smooth surface representations using the quad patch network as input and based at least in part on a smallest dimension representable by a geometry modeling kernel of a computer aided design program; and combining the one or more locally refinable smooth surface representations with the one or more modelled solids to form a second 3D model that is watertight at the one or more smooth boundary curves.Type: ApplicationFiled: April 18, 2019Publication date: May 14, 2020Inventors: Martin Cvetanov Marinov, Marco Amagliani, Peter Hugh Charrot
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Publication number: 20180255146Abstract: To represent the indirect lifecycle binding between the validity of data for a given topic, and the presence of sessions responsible for updating the data associated with that topic, sessions may register a policy referred to herein as a “session will” against specific nodes in the topic tree maintained by a data distribution system server. A session will binds the lifecycle of the topic node to that of the registering session. When a session that is responsible for updating a particular topic is disconnected, the data distribution system server initiates actions in accordance with the session will to determine how to manage updating the topic and the sub-topics in the topic path.Type: ApplicationFiled: October 17, 2016Publication date: September 6, 2018Inventors: Philip Allan George Aston, Peter Hughes, Patrick Joseph Walsh
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Publication number: 20170288065Abstract: A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination trenches. The asymmetric trench structure has a gate electrode on one side of the trench to turn on and off the channel of the MOS structure effectively and a field plate structure on the other side with field dielectric sufficiently thick in order to sustain the high electric field during the reverse bias condition.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Applicant: Diodes IncorporatedInventors: Peter Hugh Blair, Lee Spencer Riley
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Patent number: 9681814Abstract: Apparatuses and methods (including methods of using such apparatuses) for de-noising electrocardiograms (ECGs) by manually or automatically adjusting the amount of filtering of an ECG signal. For example, real-time ECG signals may be filtered by combining in a weighted fashion an unfiltered portion of an ECG (or a filtered portion of the same ECG) with the same portion of the ECG that has been filtered. The weighting may be adjusted manually and/or automatically. Also described herein are methods for real-time filtering of ECG signals using a combination of filtering techniques including filtering to correct baseline wander, Savitzky-Golay denoising, and threshold smoothing. Multiple filtering techniques may be combined in a weighed manner to provide signal de-noising.Type: GrantFiled: December 18, 2015Date of Patent: June 20, 2017Assignee: Alivecor, Inc.Inventors: Conner Daniel Cross Galloway, Alexander Vainius Valys, Nicholas Peter Hughes, David E. Albert
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Patent number: 9655297Abstract: A scraper body adapted to be attached to a furrow opener assembly with a disc rotatably mounted on an arm and oriented at a horizontal angle to create a disc furrow. The scraper body has an attachment body portion adapted to be attached to the furrow opener assembly such that a forward scraping edge of the scraper body scrapes soil from the disc face. A wing member extends from a lower rear portion of the scraper body, and has a top wing member edge oriented in alignment with the disc furrow and with the operating travel direction. Right and left wings extending downward and outward from the top wing member edge to bottom wing edges located above a bottom edge of the disc such that in operation the wings push soil to corresponding right and left sides of the disc furrow to create right and left wing furrows.Type: GrantFiled: October 21, 2014Date of Patent: May 23, 2017Inventor: Peter Hugh Barton