Patents by Inventor Peter J. Hopper

Peter J. Hopper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7298599
    Abstract: A snapback ESD protection network coupled across first and second integrated circuit pads and including first and second snapback devices, such as SCR devices, with the second device having a turnoff current ITOFF which is greater than the turnoff current of the first device. Each of the snapback devices has an anode terminal and a cathode terminal, with the first device anode and cathode terminals being coupled to the respective first and second integrated circuit pads through a first effective series resistance and the second device being coupled to the respective first and second integrated circuit pads through a second effective series resistance, with the first effective series resistance being smaller than the second so as to cause the first and second snapback devices to tend to turn on at about the same time at the beginning of an ESD event. The differences in turnoff current cause the second snapback device to turn off prior to the first snapback device at the conclusion of an ESD event.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: November 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski, Philip Lindorpher
  • Patent number: 7298653
    Abstract: In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: November 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Yuri Mirgorodski
  • Patent number: 7285805
    Abstract: In a low voltage ESD protection device, an extra control electrode is created by not connecting the n+ drain and p+ emitter regions of the LVTSCR, and controlling the control electrode by means of a diode connected NMOS.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: October 23, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Patent number: 7268410
    Abstract: Improvements in the level of integration of a core buck and/or boost DC-DC voltage regulator sub-circuit lead to a lower manufacturing cost structure, an improved performance from lessened intrinsic parasitic resistance, a smaller die size and, thus, higher wafer yield. Further, by integrating certain components on-chip, the cost and complexity of the conventional hybrid circuit implementation is improved.
    Type: Grant
    Filed: January 24, 2005
    Date of Patent: September 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Robert Drury
  • Patent number: 7268398
    Abstract: In an NMOS device, the turn-on voltage or the triggering voltage is reduced by adding an NBL connected to an n-sinker and contacted through an n+ region, which is connected to a bias voltage. The bias voltage may be provided by the drain contact or by a separate bias voltage.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: September 11, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper
  • Patent number: 7262401
    Abstract: An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: August 28, 2007
    Assignee: Eastman Kodak Company
    Inventors: Peter J. Hopper, Philipp Lindorfer, Mark W. Poulter, Yuri Mirgorodski
  • Patent number: 7259411
    Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: August 21, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Yuri Mirgorodski, Vladislav Vashchenko, Peter Johnson
  • Patent number: 7250842
    Abstract: A very, very low resistance micro-electromechanical system (MEMS) inductor, which provides resistance in the single-digit milliohm range, is formed by utilizing a single thick wide loop of metal formed around a magnetic core structure. The magnetic core structure, in turn, can utilize a laminated Ni—Fe structure that has an easy axis and a hard axis.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: July 31, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter Johnson, Peter J. Hopper, Kyuwoon Hwang, Robert Drury
  • Patent number: 7250841
    Abstract: A micro-electromechanical system (MEMS) inductor is formed in a saucer shape that completely surrounds a magnetic core structure which is formed from a ferromagnetic material. In addition, an array of MEMS inductors can be formed by dividing up the saucer-shaped MEMS inductor into a number of electrically-isolated MEMS inductor wedges.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: July 31, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Philipp Lindorfer
  • Patent number: 7239712
    Abstract: An inductor-based integrated MEMS microphone and a method of making the microphone is provided. The microphone structure includes a vibrating inductor that is suspended over another stationary inductor such that the magnetic field induced from one inductor induces an electrical potential across the other. The stationary inductor is embedded in a dielectric material that is etched out over the stationary inductor to provide the cavity over which the vibrating inductor is suspended.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: July 3, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Robert Drury, Peter J. Hopper, Michael Mian, Peter Johnson
  • Patent number: 7238553
    Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the emitter of one transistor adjacent to the tails of the sinker down region of the other transistor.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: July 3, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Andy Strachan, Peter J. Hopper, Philipp Lindorfer
  • Patent number: 7233521
    Abstract: A storage device that is capable of receiving an analog signal and storing it as a digital signal. The storage device includes an input node configured to receive an analog input voltage and two non-volatile storage cells. A second non-volatile memory cell is coupled to receive the analog input signal from the input node. The second non-volatile memory cell is capable of being programmed to a one of a plurality of programming states. The first non-volatile memory cell, which is coupled to the second non-volatile memory cell, is also capable of being programmed to one of a plurality of programming states. During operation, the second non-volatile memory cell and the first non-volatile memory cell are both programmed to a selected second programming state indicative of the magnitude of the analog input voltage. The first programming state and the second programming state are together are indicative of a digital value commensurate with the magnitude of the analog input voltage.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: June 19, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Yuri Mirgorodski, Peter J. Hopper, Vladislav Vashshenco, Philipp Lindorfer
  • Patent number: 7223680
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: May 29, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 7221036
    Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: May 22, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
  • Patent number: 7221608
    Abstract: The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device under elevated voltage. To minimize power consumption, and thus overheating, in the “on” state, a pulsed mode operation is combined with dV/dt triggering powering the device at a constant Vdd pulse amplitude.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: May 22, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
  • Patent number: 7218555
    Abstract: The integration period of an imaging cell, or the time that an imaging cell is exposed to light energy, is substantially increased by utilizing a single-poly, electrically-programmable, read-only-memory (EPROM) structure to capture the light energy. Photogenerated electrons are formed in the channel region of the EPROM structure from the light energy. The photogenerated electrons are then accelerated into having ionizing collisions which, in turn, leads to electrons being injected onto the floating gate of the EPROM structure at a rate that is proportionate to the number of photons captured by the channel region.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: May 15, 2007
    Assignee: Eastman Kodak Company
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Robert Drury
  • Patent number: 7217966
    Abstract: A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: May 15, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
  • Patent number: 7209503
    Abstract: An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: April 24, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Yuri Mirgorodski
  • Patent number: 7202538
    Abstract: A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: April 10, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Robert Drury
  • Patent number: 7196361
    Abstract: In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: March 27, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Willem Kindt, Peter J. Hopper