Abstract: A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.

Abstract: A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.

Abstract: An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits is disclosed. The integrated circuit includes a plurality of regulator circuits, each of the regulator circuits having an input node configured to receive a plurality of pulsed input signals having a predetermined duty cycle and a plurality of inductor windings associated with each of the plurality of regulator circuits respectively. The integrated circuit also includes a core array having a plurality of core elements. The plurality of core elements are positioned adjacent to and magnetically coupled with one or more of the plurality of inductor windings. An output node is electrically coupled to the plurality of inductor windings. The output signal at the output node is the sum of the instantaneous voltage on each of the inductor windings associated with the plurality of regulator circuits respectively.

Abstract: An on-chip inductor structure includes top and bottom metal plates that are formed to surround a conductor coil formed between the top and bottom plates, but is separated therefrom by intervening dielectric material. The top and bottom plates are preferably formed from a ferromagnetic alloy, e.g. Permalloy, and are subdivided into a plurality of space-apart segments, thereby reducing eddy currents. The number of segments is optimized based upon the process technology utilized to fabricate the structure. Preferably, a finite gap is formed between the top plate and the bottom plate, the height of the gap being chosen to adjust the total inductance of the structure.

Abstract: A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.

Abstract: A hybrid method of fabricating magnetic core elements of an on-chip inductor structure addresses issues associated with conventional bottom up and damascene magnetic core plating techniques. The process uses two seed layers: a low resistance seed layer that solves the IR drop problem associated with the damascene plating techniques and a high resistance seed layer that is local to magnetic core features thus avoiding eddy current related performance degradation associated with the bottom up techniques.

Abstract: A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.

Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

Abstract: In an ESD protection structure, dual direction ESD protection is provided by forming an n-well isolation ring around an NMOS device so that the p-well in which the NMOS drain is formed is isolated from the underlying p-substrate by the n-well isolation ring. By forming the n-well isolation ring the p-n-p-n structure of an embedded SCR for reverse ESD protection is provided. The width of the n-well isolation ring and its spacing from the NMOS drain are adjusted to provide the desired SCR parameters.

Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.

Abstract: An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.

Abstract: In a fuse-based programmable circuit block, the poly-fuse is burned out by making use of a snapback device connected in series with the poly-fuse.

Abstract: A pressure sensing system formed in a monolithic semiconductor substrate. The pressure sensing system comprises a pressure sensing device formed on the monolithic semiconductor substrate. The pressure sensing device is adapted to be disposed in an environment for developing an electrical pressure signal corresponding to the pressure in the environment. The system includes driver circuitry formed in the monolithic semiconductor substrate. The driver circuitry is responsive to input electrical signal for generating an output pressure signal. A conductive interconnect structure formed in the monolithic semiconductor substrate to electrically connects the pressure sensing device to the driver circuitry such that electrical pressure signals developed by the pressure sensing device are provided as input electrical signals to the driver circuitry.

Abstract: A method is provided for forming the ferromagnetic core of an on-chip inductor structure. In accordance with the method, a static, permanent magnet is placed in proximity to a semiconductor wafer upon which the ferromagnetic core is being electroplated. The permanent magnet is place such that the magnetic field is orthogonal to the wafer. The “easy” axis material is that plated parallel parallel to the magnet's field and saturates at a lower applied field. The “hard” axis is that plated perpendicular to the applied magnetic filed and saturates later, at a higher current level. This plating approach results in optimum magnetic alignment of the ferromagnetic core so as to maximize both the field strength/magnetic flux slope and magnitude before magnetic material saturation occurs.

Abstract: Feedback between the floating gate voltage and a high erase voltage is utilized in the erase operation of a non-volatile memory (NVM) cell. Erasing stops when the floating gate voltage reaches the threshold voltage of the controlling transistor, making the variability of the NVM cell's threshold voltage the same as a regular device in the integrated circuit structure, thereby reducing the significant threshold voltage variability in erased NVM cells.

Abstract: A wireless tire pressure sensing system based upon a Schrader valve design is provided. The system includes a valve body, a valve pin and a compression element for sealing engaging the valve body and the valve pin to maintain tire pressure. A pressure sensing device mounted within the valve body and connected to valve pin senses the pressure within the tire and provides its signal to the valve pin. The valve pin is adapted as a component of an antenna that transmits a wireless pressure signal to a remote receiver/transmitter mounted on the vehicle. The receiver/transmitter transmits a corresponding signal to a vehicle control system that generates a warning signal when the tire pressure is below a threshold safety value.

Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.

Abstract: The sensitivity of a MEMS microphone is substantially increased by using a portion of the package that holds the MEMS microphone as the diaphragm or a part of the diaphragm. As a result, the diaphragm of the present invention is substantially larger, and thus more sensitive, than the diaphragm in a comparably-sized MEMS microphone die.

Abstract: An apparatus and method for using anti-fuse bond pads used to provide trimmed resistor values to the input terminals of circuits on an integrated circuit die. The apparatus and method comprises fabricating on a semiconductor integrated circuit a resistive network. The resistive network includes a first terminal, a second terminal and a resistor coupled between the two terminals. An anti-fuse bond pad and a trimming resistor are coupled between the first terminal and the second terminal. The trimming resistor is configured to be electrically coupled between the first terminal and the second terminal when a ball bond is formed on the anti-fuse bond pad. In various embodiments, a plurality of the anti-fuse bond pads and trimming resistors may be coupled between the two terminals. By selectively forming ball bonds on the plurality of anti-fuse bond pads, the resistance of the network can be selectively trimmed as needed.