Patents by Inventor Peter J. Klim
Peter J. Klim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090096486Abstract: A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.Type: ApplicationFiled: February 11, 2008Publication date: April 16, 2009Inventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, Robert N. Krentler, James D. Warnock
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Patent number: 7511529Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.Type: GrantFiled: October 23, 2007Date of Patent: March 31, 2009Assignee: International Business Machines CorporationInventors: Rafik Dagher, Christopher M. Durham, Peter J. Klim
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Publication number: 20090072863Abstract: A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.Type: ApplicationFiled: October 23, 2008Publication date: March 19, 2009Applicant: INTERNATIONAL BUISNESS MACHINES CORPORATIONInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, Robert N. Krentler, James D. Warnock
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Patent number: 7472258Abstract: An SMT system has a dynamically shared GCT. Performance for the SMT is improved by configuring the GCT to allow an instruction group from each thread to complete simultaneously. The GCT has a read port for each thread corresponding to the completion table instruction/address array for simultaneous updating on completion. The forward link array also has a read port for each thread to find the next instruction group for each thread upon completion. The backward link array has a backward link write port for each thread in order to update the backward links for each thread simultaneously. The GCT has independent pointer management for each thread. Each of the threads has simultaneous commit of their renamed result registers and simultaneous updating of outstanding load and store tag usage.Type: GrantFiled: April 21, 2003Date of Patent: December 30, 2008Assignee: International Business Machines CorporationInventors: William E. Burky, Peter J. Klim, Hung Q. Le
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Patent number: 7466164Abstract: A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.Type: GrantFiled: June 7, 2007Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, James D. Warnock
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Patent number: 7466165Abstract: A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.Type: GrantFiled: September 13, 2007Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Owen Chiang, Christopher M. Durham, Peter J. Klim, Robert N. Krentler, James D. Warnock
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Publication number: 20080303553Abstract: A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.Type: ApplicationFiled: June 7, 2007Publication date: December 11, 2008Inventors: OWEN CHIANG, Christopher M. Durham, Peter J. Klim, James D. Warnock
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Publication number: 20080303554Abstract: A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.Type: ApplicationFiled: June 3, 2008Publication date: December 11, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Owen CHIANG, Christopher M. Durham, Peter J. Klim, James D. Warnock
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Publication number: 20080265957Abstract: A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Inventors: Trong V. Luong, Hung C. Ngo, Jethro C. Law, Peter J. Klim
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Publication number: 20080267341Abstract: A high performance, low power up/down counter is set forth. The counter presented is controlled by two clock pulses, an up pulse and a down pulse, and updates all bits of the counter in parallel. These bits are then latched using a scannable pulsed limited output switching dynamic logic latch. By using a limited switch dynamic logic latch, the counter is able to utilize the speed of dynamic logic without requiring the traditional dynamic logic power. The area saved and speed gained by using a dynamic latch is significant compared to a typical edge-triggered flip-flop. Additionally, by computing all the next count state bits in parallel, the counter reduces an overall count computation delay by eliminating the counter ripple.Type: ApplicationFiled: April 25, 2007Publication date: October 30, 2008Inventors: Jethro C. Law, Trong V. Luong, Hung C. Ngo, Peter J. Klim
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Publication number: 20080229260Abstract: A design structure for tuning an integrated circuit design holds a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizes transistors forming a register within the integrated circuit design and thereafter optimizes transistors forming one or more clock buffers coupled to the reference clock signal.Type: ApplicationFiled: May 30, 2008Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORP.Inventors: CHRISTOPHER M. DURHAM, Peter J. Klim, Robert N.L. Krentler
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Publication number: 20080219063Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.Type: ApplicationFiled: May 22, 2008Publication date: September 11, 2008Inventors: Michael J. Lee, Jose A. Paredes, Peter J. Klim, Sam G. Chu
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Publication number: 20080215941Abstract: A design structure embodied in a machine readable medium used in a design process, includes a circuit for data storage. The circuit includes a double edge clock generation circuit for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock; a scan clock generation circuit for generating first and second scan clock signals; a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, the scannable pulse flip-flop circuit including a scan input and a scan output connected with the internal storage node, and receptive to the pulse clock signal and the scan clock signals. The scannable pulse flip-flop circuit is configured to be operable in a function mode of operation and a scan mode of operation.Type: ApplicationFiled: May 19, 2008Publication date: September 4, 2008Applicant: International Business Machines CorporationInventors: Christopher M. Durham, Jenny Fan, Peter J. Klim, Robert N. Krentler
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Patent number: 7414436Abstract: A circuit that has a limited switch dynamic logic gate having a front end logic circuit and a latch. The output of the front end logic circuit is connected to an input of the latch, and the front end logic circuit evaluates a set of input signals applied to the front end logic circuit to generate an output signal. The latch receives and holds the output signal. The circuit also has a logic circuit having an output connected to a clock input in the front end logic circuit. The logic circuit generates a modified clock signal in response to receiving a clock signal from a clock source, and the modified clock signal has a duration that provides a minimum period of time for the front end logic to evaluate the set of input signals and generate the output signal.Type: GrantFiled: October 24, 2007Date of Patent: August 19, 2008Assignee: International Business Machines CorporationInventors: Peter J. Klim, Jethro C. Law, Trong V. Luong, Abraham Mathews
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Publication number: 20080123458Abstract: Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.Type: ApplicationFiled: July 19, 2006Publication date: May 29, 2008Applicant: International Business Machines CorporationInventors: Zhibin Cheng, Satyajit Dutta, Peter J. Klim
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Patent number: 7379348Abstract: A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.Type: GrantFiled: January 26, 2006Date of Patent: May 27, 2008Assignee: Internatioanl Business Machines CorporationInventors: Michael J. Lee, Jose A. Paredes, Peter J. Klim, Sam G. Chu
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Patent number: 7366036Abstract: A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage supply signal is supplied when the load is in full operational mode whereas the reduce voltage supply signal is provided when the load is in a sleep mode. As a consequence, power dissipated in the load is reduced.Type: GrantFiled: January 13, 2006Date of Patent: April 29, 2008Assignee: International Business Machines CorporationInventors: Zhibin Cheng, Satyajit Dutta, Peter J. Klim
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Publication number: 20080082882Abstract: A circuit for data storage is presented. The circuit includes clock generation circuits for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock and first and second scan clock signals. The circuit further includes a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, and a scan input and a scan output that are also connected with the internal storage node. In a function mode of operation, the first and second scan clock signals are held at a logic level to allow data to pass from the data input to the internal storage node at the first clock pulse and from the internal storage node to the data output at the second clock pulse signal.Type: ApplicationFiled: September 13, 2006Publication date: April 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher M. Durham, Jenny Fan, Peter J. Klim, Robert N. Krentler
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Publication number: 20080016475Abstract: A method of tuning an integrated circuit design includes holding a reference clock signal constant across the integrated circuit design and, while the reference clock signal is held constant, optimizing transistors forming a register within the integrated circuit design and thereafter optimizing transistors forming one or more clock buffers coupled to the reference clock signal.Type: ApplicationFiled: July 13, 2006Publication date: January 17, 2008Inventors: Christopher M. Durham, Peter J. Klim, Robert N. L. Krentler
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Publication number: 20070279097Abstract: Methods and apparatuses to decrease power consumption of interconnecting devices in integrated circuits are disclosed. Embodiments comprise a method to reduce power consumption in integrated circuits by generating full and reduced swing signals at an output of a driver module in response to a control signal during and deactivating one or more elements to conserve power after an input signal remains unchanged for a period of time. Another embodiment comprises an apparatus to reduce power consumption in a circuit, the embodiment comprising a swing module coupled with a swing selector and an output controller. The swing module may generate full or low swing signals depending on the state of the swing selector. The output controller may increase the output impedance of the swing module after an input signal to the swing module remains unchanged for a quantity of time. Various apparatus embodiments include portable computing devices and cellular telephones.Type: ApplicationFiled: May 31, 2006Publication date: December 6, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhibin Cheng, Satyajit Dutta, Peter J. Klim