Abstract: A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Abstract: Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

Abstract: A system and method for routing orders for financial instruments among permissioned users is provided. Orders for financial instruments are monitored from a first user. Each order includes a first price per unit component, and a first unit quantity, and the orders comprise undisclosed liquidity. The first user has one or more permissioned users, and the system and method monitors reciprocal orders for financial instruments from each of the one or more permissioned users. Each reciprocal order includes a second price per unit component and a second unit quantity, the first and second price per unit components having overlapping values, and the reciprocal orders comprise undisclosed liquidity that has not been sent to any trade execution entity.

Abstract: Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

Abstract: A computerized system and method for placing orders for financial instruments with an exchange or alternative trading system is provided. In accordance with this embodiment, updated order book information is received from each of a plurality of trade execution entities. An order for a first financial instrument of the plurality of financial instruments is received from a first user. The order includes a first price per unit component, and a first unit quantity. The first unit quantity includes a disclosed liquidity quantity and an undisclosed liquidity quantity. The order, including the disclosed liquidity quantity and the undisclosed liquidity quantity, is sent to a first one of the plurality of trade execution entities for execution. A reciprocal order for the first financial instrument that does not require that the trade execution entity be the first one of the trade execution entities is received from a second user.

Abstract: A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Abstract: An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Abstract: An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

Abstract: An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Abstract: Multiple damascene layers in integrated circuits can form several advantageous designs or components that may lower cost or increase performance of certain designs. In embodiments for power bus signals, multiple damascene layers may be used to form traces with increased power capacity and lower cost. In other embodiments, multiple damascene layers may be used to form components such as capacitors and inductors with increased performance.

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

Abstract: A process for selectively reinforcing portions of a low k dielectric material which comprises first forming a low k dielectric layer, then forming openings in the low k layer in portions of the low k layer needing reinforcement, and then filling the openings with reinforcing material, preferably reinforcing material having a higher Young's modulus of elasticity than the low k dielectric material. Such selective reinforcement of certain portions of low k dielectric material may comprise selectively reinforcing the low k dielectric material beneath the bonding pads, with reinforcing material. The low k dielectric material may be reinforced by openings in the low k dielectric material formed beneath portions of the low k dielectric layer where a capping layer will be formed over the low k dielectric material. Subsequent formation of the capping layer will simultaneously fill the openings with capping material, which may then also function as reinforcement material in the openings.

Abstract: Metalorganic precursors for deposition of strontium tantalum and strontium niobium oxides by MOCVD techniques have the formula Sr[M(OR1)6-xLx]2 wherein x is form 1 to 6; M is Ta or Nb; R1 is a straight or branched chain alkyl group; and L is an alkoxide group.

Abstract: Zirconium precursors for use in depositing thin films of or containing zirconium oxide using an MOCVD technique have the following general formula: Zrx(OR)yL, wherein R is an alkyl group; L is a &bgr;-diketonate group; x=1 or 2; y=2, 4 or 6; and z=1 or 2.

Abstract: Zirconium precursors for use in depositing thin films of or containing zirconium oxide using an MOCVD technique have the following general formula: Zr x (OR) y L z wherein R is an alkyl group; L is a 2-diketonate group; x=1 or 2; y=2, 4 or 6; and z=1 or 2.

Abstract: Provided is a transistor device, and a process for fabricating such a device, in which a top portion of a polysilicon gate electrode is removed and replaced by a low resistance metal material using a damascene process. Gate electrodes in accordance with the present invention provide improved conductivity over conventional polysilicon and silicide-capped polysilicon gate electrodes, due to the low resistivity of the metal, but do not have the drawbacks associated with the complete removal and replacement of polysilicon with a metal.

Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.

Abstract: Provided is a transistor device, and a process for fabricating such a device, in which a top portion of a polysilicon gate electrode is removed and replaced by a low resistance metal material using a damascene process. Gate electrodes in accordance with the present invention provide improved conductivity over conventional polysilicon and silicide-capped polysilicon gate electrodes, due to the low resistivity of the metal, but do not have the drawbacks associated with the complete removal and replacement of polysilicon with a metal.