Patents by Inventor Peter J. Wright

Peter J. Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5949710
    Abstract: A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconnect line (220). The configured state of the programmable interconnect junction is detected directly, and memory cell detection circuitry such as sense amplifiers are not needed during normal operation. Full-rail voltages may be passed from the first interconnect line and the second interconnect line.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: September 7, 1999
    Assignee: Altera Corporation
    Inventors: Christopher J. Pass, James D. Sansbury, Raminda U. Madurawe, John E. Turner, Rakesh H. Patel, Peter J. Wright
  • Patent number: 5903042
    Abstract: A method of integrating a low aspect ratio antifuse into low capacitance interconnect levels which involves fabrication of an antifuse base which is self-aligned to either a lower interconnect level or the antifuse dielectric. The method provides maximum allowable registration tolerance for the antifuse onto its base without incurring any increase in the pitch of the interconnect. The antifuse base is required to minimize the capacitance between the lower and upper interconnect levels. This is accomplished by providing over a lower interconnect pattern, such as, for example, aluminum over titanium tungstide (TiW), a barrier metal, such as, for example, TiW. The barrier metal separates one of the interconnect layers from the amorphous silicon dielectric. The barrier metal also acts as a raised base for the antifuse, providing increased spacing between the upper and lower interconnect patterns, thereby minimizing the capacitance therebetween.
    Type: Grant
    Filed: June 12, 1997
    Date of Patent: May 11, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Siang Ping Kwok, Peter J. Wright
  • Patent number: 5764569
    Abstract: Disclosed is a method and apparatus for charge gain characterization of non-volatile memory cells. The test structure of the present invention includes an array of non-volatile memory cells similar to that of the proposed product, but having the control gates of some or all of the cells of the array linked to form a common floating gate. In this way, charge leakage through any cell so linked will accrue in the common floating cell. Any such charge gain will be detectable through a variety of possible structures.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: June 9, 1998
    Assignee: Altera Corporation
    Inventor: Peter J. Wright
  • Patent number: 5532188
    Abstract: A method is disclosed for performing global planarization of the top layer of a structure having multiple patterned layers, during fabrication of an integrated circuit (10). An integrated circuit fabricated using the method is also disclosed. The method involves globally planarizing an integrated circuit (10) having a plurality of patterned layers (14, 18) interleaved with a plurality of unpatterned layers (16, 20). Each of the patterned layers (14, 18) is associated with a pattern mask (22, 24). The topmost layer (20) can be an unpatterned layer. Next, the pattern masks (22, 24) are combined to form a planarizing block mask (44) by merging a weighted inverse spatial interpolation of each pattern mask (22, 24). A planarizing block layer (60) is then formed on top of the topmost layer (20) using the planarizing block mask (44). Next, an unpatterned planarizing film layer (62) is formed on top of the planarizing block layer (60).
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: July 2, 1996
    Inventor: Peter J. Wright
  • Patent number: 4509997
    Abstract: There is provided a method of producing inorganic thin films by metal inorganic chemical vapor deposition. The method comprises forming a vapor stream comprising a vapor mixture of an organometallic compound and a heterocyclic organic compound incorporating a group V or group VI element, and thermally decomposing the mixture on a heated substrate to form an inorganic layer. The heterocyclic compound may be an aliphatic or aromatic ring compound. The mixture may include vapors appropriate for deposition of ternary or higher order compounds, and/or for introducing dopants.
    Type: Grant
    Filed: October 18, 1983
    Date of Patent: April 9, 1985
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Brian Cockayne, Richard J. M. Griffiths, Peter J. Wright
  • Patent number: 4496610
    Abstract: A method in which a phosphor film of manganese doped zinc chalcogenide is produced by chemical vapor deposition from alkyl zinc vapor and the gaseous hydride of the chalcogen. The manganese dopant is introduced uniformly during deposition by decomposition of tricarbonyl alkylcyclopentadienyl manganese: ##STR1## where here R denotes the alkyl radical. Preferably dimethyl zinc and tricarbonyl methylcyclopentadienyl manganese are used.The phosphor produced may be one of the following manganese doped compounds: zinc sulphide, zinc selenide, zinc sulphur selenide, zinc oxy-sulphide, zinc oxy-selenide or zinc cadmium sulphide.
    Type: Grant
    Filed: March 22, 1983
    Date of Patent: January 29, 1985
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventors: Alan F. Cattell, Brian Cockayne, Peter J. Wright, John Kirton
  • Patent number: 4328301
    Abstract: A photographic assembly for the photographic diffusion transfer process is provided wherein a stripping layer is used consisting of a graft copolymer of gelatin which has been substantially fully reacted with a dicarboxylic acid anhydride selected from phthalic anhydrides, succinic anhydrides, glutaric anhydrides and a monomer of a vinyl ester, a vinyl ether, an acrylic ester, an acrylic ether, a methacrylic ester or a methacrylic ether or a mixture thereof. These stripping layers exhibit good dry adhesion to the emulsion layer and to the mordant layer and moderate wet adhesion.
    Type: Grant
    Filed: September 18, 1980
    Date of Patent: May 4, 1982
    Assignee: Ciba-Geigy AG
    Inventor: Peter J. Wright
  • Patent number: 4278749
    Abstract: A photographic material which comprises a receiving element for transferred dyes is provided. The receiving element comprises a support having coated thereon a mordant layer which is made from a graft polymer prepared from gelatin, a monomer which when homopolymerized yields a water insoluble polymer and a monomer containing a sulphonate group which when homopolymerized yields a water soluble polymer.These receiving elements can be used for mordanting cationic dyes in photographic dye transfer processes.
    Type: Grant
    Filed: February 4, 1980
    Date of Patent: July 14, 1981
    Assignee: Ciba-Geigy AG
    Inventor: Peter J. Wright