Patents by Inventor Peter J. Zdebel
Peter J. Zdebel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7176524Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.Type: GrantFiled: February 15, 2005Date of Patent: February 13, 2007Assignee: Semiconductor Components Industries, LLCInventors: Gary H. Loechelt, Peter J. Zdebel, Gordon M. Grivna
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Patent number: 7098509Abstract: In one embodiment, a concentric ring ESD structure includes a first p-type region and a second p-type region are formed in a layer of semiconductor material. The two p-type regions are coupled together with a floating n-type buried layer. The first and second p-type regions form a back-to-back diode structure with the floating n-type buried layer. A pair of shorted n-type and p-type contact regions is formed in each of the first and second regions. An isolation region is formed between the first and second p-type regions.Type: GrantFiled: January 2, 2004Date of Patent: August 29, 2006Assignee: Semiconductor Components Industries, L.L.C.Inventors: Peter J. Zdebel, Diann Michelle Dow
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Patent number: 6953980Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.Type: GrantFiled: June 11, 2002Date of Patent: October 11, 2005Assignee: Semiconductor Components Industries, LLCInventors: Rene Escoffier, Evgueniy Stefanov, Jeffrey Pearse, Francine Y. Robb, Peter J. Zdebel
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Patent number: 6809396Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).Type: GrantFiled: November 25, 2002Date of Patent: October 26, 2004Assignee: Semiconductor Components Industries, L.L.C.Inventors: Peter J. Zdebel, Misbahul Azam, Gary H. Loechelt, James R. Morgan, Julio C. Costa
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Publication number: 20040099896Abstract: An integrated circuit (100) includes high performance complementary bipolar NPN and PNP vertical transistors (10, 20). The NPN transistor is formed on a semiconductor substrate whose surface (24) is doped to form a PNP base region (28, 70). A film (32, 34, 30) is formed on the surface with an opening (42) over an edge of the base region. A first conductive spacer (48) is formed along a first sidewall (78) of the opening to define a PNP emitter region (67) within the base region. A second conductive spacer (47) is formed along a second sidewall (76) of the opening to define a PNP collector region (66).Type: ApplicationFiled: November 25, 2002Publication date: May 27, 2004Applicant: Semiconductor Components Industries, LLC.Inventors: Peter J. Zdebel, Misbahul Azam, Gary H. Loechelt, James R. Morgan, Julio C. Costa
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Publication number: 20030228848Abstract: A filter circuit (10) is formed on a semiconductor substrate (11) formed with a trench (40) that is lined with a dielectric layer (38). A conductive material (37) is disposed in the trench and coupled to a node (62) to provide a capacitance that modifies a frequency response of an input signal (VIN) to produce a filtered signal (VOUT). An electrostatic discharge device includes an inductor (74) coupled to back to back diodes (17, 18) formed in the substrate to avalanche when a voltage on the node reaches a predetermined magnitude.Type: ApplicationFiled: June 11, 2002Publication date: December 11, 2003Applicant: Semiconductor Components Industries, LLCInventors: Rene Escoffier, Evgueniy Stefanov, Jeffrey Pearse, Francine Y. Robb, Peter J. Zdebel
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Patent number: 6610143Abstract: A method of manufacturing a semiconductor component includes forming an electrically insulative layer (220) over a semiconductor substrate where a first portion of the electrically insulative layer is located over a first region (560) of the semiconductor substrate and where a second portion of the first layer is located over a second region (550) of the semiconductor substrate. An isolation region (610) is formed in the semiconductor substrate between the first and second regions of the semiconductor substrate. After forming the isolation region, the second portion of the first layer is removed, and, after removing the second potion of the first layer, an epitaxial layer (630) is grown over the second region of the semiconductor substrate.Type: GrantFiled: January 16, 2001Date of Patent: August 26, 2003Assignee: Semiconductor Components Industries LLCInventors: Peter J. Zdebel, Julio Carlos Costa
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Publication number: 20020092463Abstract: A method of manufacturing a semiconductor component includes forming an electrically insulative layer (220) over a semiconductor substrate where a first portion of the electrically insulative layer is located over a first region (560) of the semiconductor substrate and where a second portion of the first layer is located over a second region (550) of the semiconductor substrate. An isolation region (610) is formed in the semiconductor substrate between the first and second regions of the semiconductor substrate. After forming the isolation region, the second portion of the first layer is removed, and, after removing the second potion of the first layer, an epitaxial layer (630) is grown over the second region of the semiconductor substrate.Type: ApplicationFiled: January 16, 2001Publication date: July 18, 2002Inventors: Peter J. Zdebel, Julio Carlos Costa
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Patent number: 6118171Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a base region (44) that contacts the corners (13) of the pedestal structure (16). Electrical connection to the base region (44) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).Type: GrantFiled: December 21, 1998Date of Patent: September 12, 2000Assignee: Motorola, Inc.Inventors: Robert B. Davies, Peter J. Zdebel
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Patent number: 6033231Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).Type: GrantFiled: July 24, 1998Date of Patent: March 7, 2000Assignee: Motorola, Inc.Inventors: Robert B. Davies, Andreas A. Wild, Diann M. Dow, Peter J. Zdebel, E. James Prendergast
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Patent number: 5965930Abstract: A high frequency bipolar transistor (30, 60) having reduced capacitance and inductance is formed over a substrate (61). The substrate (61) is heavily doped to form a low resistance current path. A lightly doped epitaxial layer (62) isolates the substrate (61) from layers which form the transistor. The epitaxial layer (62) is the same conductivity type as the substrate (61). A topside substrate contact (73) couples an emitter of the transistor (60) to the substrate (61). The backside of the substrate (61) is metalized and conductively attached to a leaded flag of a leadframe (51) thereby eliminating wirebond inductance in the emitter of the transistor.Type: GrantFiled: November 4, 1997Date of Patent: October 12, 1999Assignee: Motorola, Inc.Inventors: Kurt K. Sakamoto, Peter J. Zdebel, Michael G. Lincoln
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Patent number: 5920102Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying an epitaxial layer (12) and a semiconductor substrate (11). The semiconductor device (10) includes a doped region (13) that forms a PN junction with the epitaxial layer (12). The semiconductor device (10) also includes a dielectric layer (22) that has an opening (23) that exposes a portion of the doped region (13) and an opening (24) that exposes a portion of the epitaxial layer (12). The openings (23, 24) are filled with a conductive material (36, 37) to provide contacts (100, 101). Due to the presence of the PN junction, the contacts (100, 101) are capacitively coupled to each other.Type: GrantFiled: May 30, 1997Date of Patent: July 6, 1999Assignee: Motorola, Inc.Inventors: Robert B. Davies, Andreas A. Wild, Peter J. Zdebel
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Patent number: 5920095Abstract: A semiconductor device (10) is formed in a pedestal structure (16) overlying a semiconductor substrate (11). The semiconductor device (10) includes a source region (44) and a drain region (45) that contact the corners (13) of the pedestal structure (16). Electrical connection to the source region (44) and the drain region (45) is provided by a conductive layer (28) that contacts the sides (12) and corners (13) of the pedestal structure (16).Type: GrantFiled: July 30, 1997Date of Patent: July 6, 1999Assignee: Motorola, Inc.Inventors: Robert Bruce Davies, Peter J. Zdebel
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Patent number: 5886374Abstract: A process combines a high performance silicon pin diode (60) and other semiconductor devices such as transistors, resistors, and capacitors. The pin diode (60) is formed beneath an epitaxial layer (44) of the device at a depth that maximizes absorption of light having a wavelength greater than approximately 600 nanometers. Devices such as transistors are formed in the epitaxial layer (44). An integrated circuit has a substrate (41), an intrinsically doped layer (42), a buried layer (43), and an epitaxial layer (44). An isolation region (45) isolates an intrinsically doped region (46), a buried layer region (47), and the epitaxial layer region (48). The pin diode (32) has a substrate (41), an intrinsically doped region (46), and a buried layer region (47). A polysilicon region (62) provides a top side contact for the pin diode (60).Type: GrantFiled: January 5, 1998Date of Patent: March 23, 1999Assignee: Motorola, Inc.Inventors: Kurt K. Sakamoto, Peter J. Zdebel, Christopher K. Y. Chun
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Patent number: 5818098Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60, 97) that can be used to transport electrical signals across the device (10).Type: GrantFiled: February 29, 1996Date of Patent: October 6, 1998Assignee: Motorola, Inc.Inventors: Robert B. Davies, Andreas A. Wild, Diann M. Dow, Peter J. Zdebel, E. James Prendergast
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Patent number: 5808362Abstract: A graded-channel semiconductor device (10) is formed in a pedestal (12). The pedestal (12) is formed on a substrate (11) and improves the electrical characteristics of the device (10) compared to conventional device structures. The pedestal (12) has sides (13) that are bordered by a first dielectric layer (24) to provide electrical isolation. An interconnect structure (90) can be optionally formed in conjunction with the formation of the device (10). The interconnect structure (90) has a plurality of conductors (60,97) that can be used to transport electrical signals across the device (10).Type: GrantFiled: February 29, 1996Date of Patent: September 15, 1998Assignee: Motorola, Inc.Inventors: Robert B. Davies, Andreas A. Wild, Peter J. Zdebel
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Patent number: 5712501Abstract: A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.Type: GrantFiled: October 10, 1995Date of Patent: January 27, 1998Assignee: Motorola, Inc.Inventors: Robert B. Davies, Frank K. Baker, Jon J. Candelaria, Andreas A. Wild, Peter J. Zdebel
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Patent number: 5510648Abstract: An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.Type: GrantFiled: September 7, 1994Date of Patent: April 23, 1996Assignee: Motorola, Inc.Inventors: Robert B. Davies, Peter J. Zdebel, Juan Buxo
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Patent number: 5372960Abstract: An insulated gate semiconductor device (10) having a pseudo-stepped channel region (20B) between two P-N junctions (21B and 22B). The pseudo-stepped channel region (20B) is comprised of an enhancement mode portion (26B) and a depletion mode portion (28B), the enhancement mode portion (26B) being more heavily doped than the depletion mode portion (28B). One P-N junction (21B) is formed at an interface between a source region (18B) and the enhancement mode portion (26B). The enhancement mode portion (26B) has a substantially constant doping profile, thus slight variations in the placement of the source region (18B) within the enhancement region (26B) do not result in significant variations in the threshold voltage of the insulated gate semiconductor device (10). The insulated gate semiconductor device (10) is well suited for the design of low voltage circuits because of the small variations of the threshold voltage.Type: GrantFiled: January 4, 1994Date of Patent: December 13, 1994Assignee: Motorola, Inc.Inventors: Robert B. Davies, Peter J. Zdebel, Juan Buxo
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Patent number: 5154946Abstract: A method of fabricating a CMOS structure that may be integrated into a BICMOS process flow includes forming N and P type doped wells in an isolation module. A first conformal nitride layer is formed on the surface of the isolation module and portions of the nitride layer disposed over the doped wells are removed. After forming a gate oxide layer on the doped wells, a conformal polysilicon layer is formed and doped on the surface of the structure. The conformal polysilicon layer is etched into gate electrodes which are used as a mask for the self-aligned implant of first portions of source and drain regions in the doped wells. Dielectric spacers abutting the edges of the gate electrodes are formed and the implantation of second portions of the source and drain regions is self-aligned to the dielectric spacers. Following the formation of a conformal nitride layer and a conformal oxide layer, the structure is planarized and source, drain and gate contacts are formed.Type: GrantFiled: February 4, 1991Date of Patent: October 13, 1992Assignee: Motorola, Inc.Inventor: Peter J. Zdebel