Abstract: A method of forming planar isolation regions in semiconductor structures includes providing a semiconductor substrate and forming a semiconductor layer thereon. A dielectric layer comprising at least two different dielectric materials is disposed on the semiconductor layer and a trench is etched therethrough and into the semiconductor layer. Dielectric sidewalls are formed in the trench which is then filled by selectively forming depositing polycrystalline silicon therein. The semiconductor material is then at least partially oxidized to form the planar isolation region. The isolation regions disclosed herein may be used for both intradevice and interdevice isolation.

Abstract: A method of forming oppositely doped semiconductor regions includes providing a first semiconductor layer of a first conductivity type and forming a second semiconductor layer of a second conductivity type on a portion of the first layer. A third semiconductor layer is formed on the second layer and the exposed portions of the first layer. The dopant concentration of the third layer is less than the dopant concentration of the second layer so that dopant of the second conductivity type diffuses from the second layer into the portion of the third layer disposed thereabove.

Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

Abstract: A method of fabrication of a device having laterally isolated semiconductor regions. In a preferred embodiment, laterally isolated polysilicon features are created with vertical, nitride-sealed sidewalls. The nitride-sealed sidewalls formed using sidewall spacer technology eliminate oxide encroachment while further preventing the loss of dopant laterally during thermal processing. The final structure comprises polysilicon features flanked by either oxide isolation or additional polysilicon features and is planar without requiring a planarization etchback. The process is applicable to polysilicon electrodes over active areas as well as polysilicon resistors over isolation oxide.

Abstract: A method of fabricating electrodes comprises providing a semiconductor structure having doped tubs and forming a first dielectric layer of a first dielectric material thereon. A second dielectric layer of a second dielectric material is formed on the first dielectric layer and openings are formed in the second dielectric layer that extend to the first dielectric layer. A conformal semiconductor layer is formed over the entire semiconductor structure and nitride spacers are then formed in the openings on the conformal semiconductor layer. The conformal semiconductor layer is then oxidized so that only semiconductor slivers remain beneath the spacers. The spacers and the semiconductor slivers are removed as well as the portions of the first dielectric layer disposed therebeneath. Conductive electrodes which are coupled to the doped tubs are then formed in the openings.

Abstract: A method of fabricating a semiconductor structure having self-aligned diffused junctions is provided wherein a first dielectric layer, a doped semiconductor layer and a second dielectric layer are formed on a semiconductor substrate. An opening extending to the semiconductor substrate is then formed through these layers. Undoped semiconductor spacers are formed in the opening adjacent to the exposed ends of the doped semiconductor layer and dopant is diffused from the doped semiconductor layer through the undoped semiconductor spacers and into the semiconductor substrate to form junctions therein. This provides for integrated contacts through the doped semiconductor layer.

Abstract: A method of fabricating multiple trench semiconductor structures wherein a preferred embodiment includes forming an epitaxial silicon layer on a silicon substrate and a dielectric layer on the epitaxial silicon layer. An opening is then formed which extends through the dielectric layer and into the epitaxial silicon layer. Sidewall spacers are formed in the opening and an oxide lens is formed in the opening between the sidewall spacers. The sidewall spacers are then removed and trenches are formed in the opening where the sidewall spacers were formerly disposed.

Abstract: The degradation of the low current gain, which is exhibited during emitter-base reverse bias breakdown testing, is prevented by providing an emitter-base resistive shunt on the surface. This resistive shunt, preferably made of silicon nitride. utilizes surface recombination to reduce the low current gain permanently, thus a degradation is not exhibited upon testing.

Abstract: A planarized dielectric isolation region for semiconductor devices and integrated circuits is created by providing a semiconductor substrate, providing on the substrate an oxide/nitride mask with an opening for defining the isolation region and a closed portion for defining the desired semiconductor islands, anisotropically etching a trench into the semiconductor substrate, isotropically etching the substrate so as to slightly undercut the oxide/nitride mask, thermally oxidizing the substrate to form a thin oxide layer on the bottom and sidewall of the trench wherein the outer surface of the thermal oxide approximately lines up with the edge of the oxide/nitride mask at the top of the trench sidewall, filling the trench with a conformal deposited material (preferably a dielectric), providing a mask over the conformal material which is the complement to the trench etch or island mask but of smaller lateral dimensions so as to cover those portions of the conformal layer which do not rise up over the semiconduct

Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a process which produces small device areas without relying upon restrictive photolithography tolerances. The process uses four polycrystalline silicon layers to fabricate and contact the device regions, to achieve a relatively planar structure, and to reduce the size of device regions below normal photolithographic tolerances. The process uses a master mask to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. Means and methods for many types of devices such as complementary lateral and vertical bipolar transistors, JFETs, Sits, MOSFETs, resistors, diodes, capacitors and other devices which can be simultaneously fabricated are also described.

Abstract: A means and method for forming a single tub transistor, such as for example a vertical NPN bipolar transistor surrounded by an isolation wall, is described. Multiple polysilicon and dielectric layers are employed in conjunction with a master mask and with isotropic and anisotropic etching procedures to define the contacts and active regions of the device without resorting to precision alignments. Sub-micron lateral device contacts are easily achieved even with comparatively coarse lithographic methods through use of sidewall spacers for controlled narrowing of critical device openings. The finished device is especially compact, has low resistance contacts for its size, and provides very high speed operation.

Abstract: A process is disclosed for fabricating improved integrated circuit devices. In accordance with one embodiment of the invention integrated devices are fabricated by a four layer poly process which produces small device areas without relying upon restrictive photolithography tolerances. A master mask is used to define the basic footprint of the device in combination with easy to align block-out masks in each lithography step. A double implant doping process is used to control the Gummel number in the base of bipolar transistors and like regions. A shallow implant is placed in a screen oxide and a deep implant into the desired base location. The dopant saturated screen oxide prevents segregation of the deep base implant during subsequent heat treatment. The double implant process applies to many desired device structures.