Patents by Inventor Peter Javorka

Peter Javorka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys
    Patent number: 8343826
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: January 1, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Strain enhancement in transistors comprising an embedded strain-inducing semiconductor alloy by corner rounding at the top of the gate electrode
    Patent number: 8338892
    Abstract: In MOS transistor elements, a strain-inducing semiconductor alloy may be embedded in the active region with a reduced offset from the channel region by applying a spacer structure of reduced width. In order to reduce the probability of creating semiconductor residues at the top area of the gate electrode structure, a certain degree of corner rounding of the semiconductor material may be introduced, which may be accomplished by ion implantation prior to epitaxially growing the strain-inducing semiconductor material. This concept may be advantageously combined with the provision of sophisticated high-k metal gate electrodes that are provided in an early manufacturing stage.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 25, 2012
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Roman Boschke, Maciej Wiatr, Peter Javorka
  • Method of Forming Sidewall Spacers Having Different Widths Using a Non-Conformal Deposition Process
    Publication number: 20120309182
    Abstract: Disclosed herein is a method of forming sidewall spacers for a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate. performing a non-conformal deposition process to deposit a layer of spacer material above the gate electrode structure and performing an anisotropic etching process on the layer of spacer material to define a first sidewall spacer proximate a first side of the gate electrode structure and a second sidewall spacer proximate a second side of the gate electrode structure, wherein the first and second sidewall spacers have different widths.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Peter Javorka
  • PERFORMANCE ENHANCEMENT IN TRANSISTORS BY PROVIDING AN EMBEDDED STRAIN-INDUCING SEMICONDUCTOR MATERIAL ON THE BASIS OF A SEED LAYER
    Publication number: 20120305995
    Abstract: In sophisticated semiconductor devices, transistors may be formed on the basis of a high-k metal gate electrode structure provided in an early manufacturing phase, wherein an efficient strain-inducing mechanism may be implemented by using an embedded strain-inducing semiconductor alloy. In order to reduce the number of lattice defects and provide enhanced etch resistivity in a critical zone, i.e., in a zone in which a threshold voltage adjusting semiconductor alloy and the strain-inducing semiconductor material are positioned in close proximity, an efficient buffer material or seed material, such as a silicon material, is incorporated, which may be accomplished during the selective epitaxial growth process.
    Type: Application
    Filed: May 30, 2012
    Publication date: December 6, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Javorka, Stephan Kronholz, Gunda Beernink
  • PMOS Threshold Voltage Control by Germanium Implantation
    Publication number: 20120302023
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Javorka, Stephan Kronholz
  • Method of Increasing the Germanium Concentration in a Silicon-Germanium Layer and Semiconductor Device Comprising Same
    Publication number: 20120280289
    Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming layer of silicon germanium on a P-active region of a semiconducting substrate wherein the layer of silicon germanium has a first concentration of germanium, and performing an oxidation process on the layer of silicon germanium to increase a concentration of germanium in at least a portion of the layer of silicon germanium to a second concentration that is greater than the first concentration of germanium.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Thilo Scheiper, Peter Javorka, Jan Hoentschel
  • Reduced Threshold Voltage-Width Dependency and Reduced Surface Topography in Transistors Comprising High-K Metal Gate Electrode Structures by a Late Carbon Incorporation
    Publication number: 20120282744
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. On the other hand, increased yield losses observed in conventional strategies may be reduced by taking into consideration the increased etch rate of the carbon-doped silicon material in the active regions. To this end, the carbon species may be incorporated after the application of at least some aggressive wet chemical processes.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter Javorka, Stephan Kronholz
  • Shallow Source and Drain Architecture in an Active Region of a Semiconductor Device Having a Pronounced Surface Topography by Tilted Implantation
    Publication number: 20120241864
    Abstract: In sophisticated semiconductor devices, a shallow drain and source concentration profile may be obtained for active regions having a pronounced surface topography by performing tilted implantation steps upon incorporating the drain and source dopant species. In this manner, a metal silicide may be reliably embedded in the drain and source regions.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Applicants: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG, GLOBALFOUNDRIES INC.
    Inventors: Martin Gerhardt, Peter Javorka, Juergen Faul
  • Stabilization of Metal Silicides in PFET Transistors by Incorporation of Stabilizing Species in a Si/Ge Semiconductor Material
    Publication number: 20120241816
    Abstract: When forming sophisticated P-channel transistors, the metal silicide agglomeration in a germanium-containing strain-inducing semiconductor alloy may be avoided or at least significantly reduced by incorporating a carbon and/or nitrogen species in a highly controllable manner. In some illustrative embodiments, the carbon species or nitrogen species is incorporated during the epitaxial growth process so as to form a surface layer of the strain-inducing semiconductor alloy with a desired nitrogen and/or carbon concentration and with a desired thickness without unduly affecting any other device areas.
    Type: Application
    Filed: March 21, 2011
    Publication date: September 27, 2012
    Applicants: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co., KG, GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Thilo Scheiper, Peter Javorka
  • Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions
    Patent number: 8274120
    Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: September 25, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andy Wei, Thorsten Kammler, Jan Hoentschel, Manfred Horstmann, Peter Javorka, Joe Bloomquist
  • REDUCING DEFECT RATE DURING DEPOSITION OF A CHANNEL SEMICONDUCTOR ALLOY INTO AN IN SITU RECESSED ACTIVE REGION
    Publication number: 20120235249
    Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • METHODS FOR FABRICATING SEMICONDUCTOR DEVICES
    Publication number: 20120202326
    Abstract: Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.
    Type: Application
    Filed: February 3, 2011
    Publication date: August 9, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan-Detlef KRONHOLZ, Peter JAVORKA, Roman BOSCHKE
  • Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys
    Publication number: 20120161250
    Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
    Type: Application
    Filed: August 4, 2011
    Publication date: June 28, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan-Detlef Kronholz, Peter Javorka, Maciej Wiatr
  • Differential Threshold Voltage Adjustment in PMOS Transistors by Differential Formation of a Channel Semiconductor Material
    Publication number: 20120153401
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.
    Type: Application
    Filed: August 3, 2011
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Peter JAVORKA, Maciej WIATR, Stephan-Detlef KRONHOLZ
  • Semiconductor device comprising isolation trenches inducing different types of strain
    Patent number: 8138571
    Abstract: By forming isolation trenches of different types of intrinsic stress on the basis of separate process sequences, the strain characteristics of adjacent active semiconductor regions may be adjusted so as to obtain overall device performance. For example, highly stressed dielectric fill material including compressive and tensile stress may be appropriately provided in the respective isolation trenches in order to correspondingly adapt the charge carrier mobility of respective channel regions.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: March 20, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Christoph Schwan, Joe Bloomquist, Peter Javorka, Manfred Horstmann, Sven Beyer, Markus Forsberg, Frank Wirbeleit, Karla Romero
  • Reduced Topography in Isolation Regions of a Semiconductor Device by Applying a Deposition/Etch Sequence Prior to Forming the Interlayer Dielectric
    Publication number: 20120025318
    Abstract: Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled.
    Type: Application
    Filed: June 7, 2011
    Publication date: February 2, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Peter Javorka, Kai Frohberg
  • Transistor With Embedded Si/Ge Material Having Reduced Offset and Superior Uniformity
    Publication number: 20120001254
    Abstract: In sophisticated semiconductor devices, a strain-inducing embedded semiconductor alloy may be provided on the basis of a crystallographically anisotropic etch process and a self-limiting deposition process, wherein transistors which may not require an embedded strain-inducing semiconductor alloy may remain non-masked, thereby providing superior uniformity with respect to overall transistor configuration. Consequently, superior strain conditions may be achieved in one type of transistor, while generally reduced variations in transistor characteristics may be obtained for any type of transistors.
    Type: Application
    Filed: January 13, 2011
    Publication date: January 5, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan Kronholz, Peter Javorka, Roman Boschke
  • Reduction of Defect Rates in PFET Transistors Comprising a Si/Ge Semiconductor Material Formed by Epitaxial Growth
    Publication number: 20110291163
    Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.
    Type: Application
    Filed: December 10, 2010
    Publication date: December 1, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stephan Kronholz, Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger
  • Method for reducing defects of gate of CMOS devices during cleaning processes by modifying a parasitic PN junction
    Patent number: 8039338
    Abstract: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Manfred Horstmann, Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff
  • Method of forming a semiconductor structure comprising a formation of at least one sidewall spacer structure
    Patent number: 8003460
    Abstract: According to an illustrative example, a method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first feature and a second feature. A material layer is formed over the first feature and the second feature. A mask is formed over the first feature. At least one etch process adapted to form a sidewall spacer structure adjacent the second feature from a portion of the material layer is performed. The mask protects a portion of the material layer over the first feature from being affected by the at least one etch process. An ion implantation process is performed. The mask remains over the first feature during the ion implantation process.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: August 23, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Wirbeleit, Rolf Stephan, Peter Javorka