Abstract: A method of forming a semiconductor device is provided including the steps of forming first and second PMOS transistor devices, wherein the first PMOS transistor devices are low, standard or high voltage threshold transistor devices and the second PMOS transistor devices are super high voltage threshold transistor devices, and wherein forming the first PMOS transistor devices includes implanting dopants to form source and drain junctions of the first PMOS transistor devices and performing a thermal anneal of the first PMOS transistor devices after implanting the dopants, and forming the second PMOS transistor devices includes implanting dopants to form source and drain junctions of the second PMOS transistor devices after performing the thermal anneal of the first PMOS transistor devices.

Abstract: A method of forming a spacer is disclosed that involves forming a layer of spacer material above an etch stop layer, performing a first main etching process on the layer of spacer material to remove some of material, stopping the etching process prior to exposing the etch stop layer and performing a second over-etch process on the layer of spacer material, using the following parameters: an inert gas flow rate of about 50-200 sscm, a reactive gas flow rate of about 3-20 sscm, a passivating gas flow rate of about 3-20 sscm, a processing pressure about 5-15 mT, a power level of about 200-500 W for ion generation and a bias voltage of about 300-500 V. A device includes a gate structure positioned above a semiconducting substrate, a substantially triangular-shaped sidewall spacer positioned proximate the gate structure and an etch stop layer positioned between the spacer and the gate structure.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

Abstract: A method for fabricating a semiconductor device includes forming first and second gate structures overlying the semiconductor substrate, and depositing a layer of a silicide-resistant material over the first and second gate structures and over the semiconductor substrate. The method further includes forming sidewall spacers from the layer of silicide-resistant material adjacent the first gate structure and removing the silicide-resistant material adjacent the sidewall spacers to expose the silicon substrate in a source and drain region. Still further, the method includes implanting conductivity determining impurities in the source and drain region, depositing a silicide forming metal, and annealing the semiconductor device to form a silicide in the source and drain region. The silicide-resistant material is not removed from over the second gate structure so as to prevent silicide formation at the second gate structure.

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.

Abstract: When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.

Abstract: One method herein includes forming a gate structure above an active area of a semiconductor substrate, forming sidewall spacer structures adjacent the gate structure, forming a masking layer that allows implantation of ions into the gate electrode but not into areas of the active region where source/drain regions for the transistor will be formed, performing a gate ion implantation process to form a gate ion implant region in the gate electrode and performing an anneal process. An N-type transistor including sidewall spacer structures positioned adjacent a gate structure, a plurality of source/drain regions for the transistor and a gate implant region positioned in a gate electrode, wherein the gate implant region is comprised of ions of phosphorous, arsenic or an implant material with an atomic size that is equal to or greater than the atomic size of phosphorous at a concentration level that falls within the range of 5e18-5e21 ions/cm3.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. In an embodiment of a method for fabricating integrated circuits, a P-type gate electrode structure and an N-type gate electrode structure are formed overlying a semiconductor substrate. The gate electrode structures each include a gate electrode that overlies a gate dielectric layer and a nitride cap that overlies the gate electrode. Conductivity determining ions are implanted into the semiconductor substrate using the P-type gate electrode structure and the N-type gate electrode structure as masks to form a source region and a drain region for the P-type gate electrode structure and the N-type gate electrode structure. The nitride cap remains overlying the N-type gate electrode structure during implantation of the conductivity determining ions into the semiconductor substrate to form the source region and the drain region for the N-type gate electrode structure.

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract: A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a channel region, a gate electrode, wherein the gate electrode is provided at least at two opposite sides of each of the one or more elongated semiconductor regions, and a layer of a stress-creating material, the stress-creating material providing a variable stress, wherein the layer of stress-creating material is arranged to provide a stress at least in the channel region of each of the one or more elongated semiconductor regions, the stress provided in the channel region of each of the one or more elongated semiconductor regions being variable.

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract: When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract: A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region.