Patents by Inventor Peter Love
Peter Love has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9727527Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: GrantFiled: June 1, 2015Date of Patent: August 8, 2017Assignee: D-Wave Systems Inc.Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul I. Bunyk, Andrew J. Berkley
-
Publication number: 20170177751Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: ApplicationFiled: January 30, 2017Publication date: June 22, 2017Inventors: William G. Macready, Geordie Rose, Thomas F.W. Mahon, Peter Love, Marshall Drew-Brook
-
Patent number: 9665539Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: GrantFiled: January 30, 2017Date of Patent: May 30, 2017Assignee: D-Wave Systems Inc.Inventors: William G. Macready, Geordie Rose, Thomas F.W. Mahon, Peter Love, Marshall Drew-Brook
-
Patent number: 9594726Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: GrantFiled: June 23, 2016Date of Patent: March 14, 2017Assignee: D-Wave Systems Inc.Inventors: William G. Macready, Geordie Rose, Thomas F. W. Mahon, Peter Love, Marshall Drew-Brook
-
Publication number: 20160371227Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: ApplicationFiled: June 23, 2016Publication date: December 22, 2016Inventors: William G. Macready, Geordie Rose, Thomas F.W. Mahon, Peter Love, Marshall Drew-Brook
-
Publication number: 20160283857Abstract: Generating a computing specification to be executed by a quantum processor includes: accepting a problem specification that corresponds to a second-quantized representation of a fermionic Hamiltonian, and transforming the fermionic Hamiltonian into a first qubit Hamiltonian including a first set of qubits that encode a fermionic state specified by occupancy of spin orbitals. An occupancy of any spin orbital is encoded in a number of qubits that is logarithmic in the number of spin orbitals, and a parity for a transition between any two spin orbitals is encoded in a number of qubits that is logarithmic in the number of spin orbitals. An eigenspectrum of a second qubit Hamiltonian, including the first set of qubits and a second set of qubit, includes a low-energy subspace and a high-energy subspace, and an eigenspectrum of the first qubit Hamiltonian is approximated by a set of low-energy eigenvalues of the low-energy subspace.Type: ApplicationFiled: November 4, 2014Publication date: September 29, 2016Inventors: Ryan Babbush, Peter Love, Alan Aspuru-Guzik
-
Patent number: 9405876Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: GrantFiled: February 21, 2014Date of Patent: August 2, 2016Assignee: D-WAVE SYSTEMS INC.Inventors: William Macready, Geordie Rose, Thomas Mahon, Peter Love, Marshall Drew-Brook
-
Publication number: 20150332164Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: ApplicationFiled: June 1, 2015Publication date: November 19, 2015Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H.S. Amin, Geordie Rose, David Grant, Miles F.H. Steininger, Paul I. Bunyk, Andrew J. Berkley
-
Patent number: 9069928Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: GrantFiled: February 7, 2014Date of Patent: June 30, 2015Assignee: D-Wave Systems Inc.Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul I. Bunyk, Andrew J. Berkley
-
Patent number: 9026574Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.Type: GrantFiled: November 15, 2012Date of Patent: May 5, 2015Assignee: D-Wave Systems Inc.Inventors: William Macready, Geordie Rose, Thomas Mahon, Peter Love, Marshall Drew-Brook
-
Publication number: 20140245249Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: ApplicationFiled: February 21, 2014Publication date: August 28, 2014Applicant: D-Wave Systems Inc.Inventors: William Macready, Geordie Rose, Thomas Mahon, Peter Love, Marshall Drew-Brook
-
Publication number: 20140229705Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: ApplicationFiled: February 7, 2014Publication date: August 14, 2014Applicant: D-Wave Systems Inc.Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul I. Bunyk, Andrew J. Berkley
-
Patent number: 8700689Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: GrantFiled: June 16, 2010Date of Patent: April 15, 2014Assignee: D-Wave Systems Inc.Inventors: William Macready, Geordie Rose, Thomas Mahon, Peter Love, Marshall Drew-Brook
-
Patent number: 8686751Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: GrantFiled: September 10, 2012Date of Patent: April 1, 2014Assignee: D-Wave Systems Inc.Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul Bunyk, Andrew J. Berkley
-
Patent number: 8560282Abstract: Systems, methods and apparatus for factoring numbers are provided. The factoring may be accomplished by creating a factor graph, mapping the factor graph onto an analog processor, initializing the analog processor to an initial state, evolving the analog processor to a final state, and receiving an output from the analog processor, the output comprising a set of factors of the number. The factoring may be accomplished by generating a logic circuit representation of the factoring problem, such as a multiplication circuit, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s).Type: GrantFiled: August 3, 2010Date of Patent: October 15, 2013Assignee: D-Wave Systems Inc.Inventors: William G. Macready, Geordie Rose, Peter Love
-
Publication number: 20130007087Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: ApplicationFiled: September 10, 2012Publication date: January 3, 2013Applicant: D-WAVE SYSTEMS INC.Inventors: Alec Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul Bunyk, Andrew J. Berkley
-
Patent number: 8283943Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: GrantFiled: August 15, 2011Date of Patent: October 9, 2012Assignee: D-Wave Systems Inc.Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul Bunyk, Andrew J. Berkley
-
Publication number: 20110298489Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: ApplicationFiled: August 15, 2011Publication date: December 8, 2011Applicant: D-WAVE SYSTEMS INC.Inventors: Alec Maassen van den Brink, Peter Love, Mohammad H.S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul Bunyk, Andrew J. Berkley
-
Publication number: 20110231462Abstract: Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a Boolean logic circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A quantum processor may include multiple sets of qubits, each set coupled to respective annealing signal lines such that dynamic evolution of each set of qubits is controlled independently from the dynamic evolutions of the other sets of qubits.Type: ApplicationFiled: June 16, 2010Publication date: September 22, 2011Applicant: D-WAVE SYSTEMS INC.Inventors: William Macready, Geordie Rose, Thomas Mahon, Peter Love, Marshall Drew-Brook
-
Patent number: 8008942Abstract: Analog processors for solving various computational problems are provided. Such analog processors comprise a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices. The analog processors further comprise bias control systems each configured to apply a local effective bias on a corresponding quantum device. A set of coupling devices in the plurality of coupling devices is configured to couple nearest-neighbor quantum devices in the lattice. Another set of coupling devices is configured to couple next-nearest neighbor quantum devices. The analog processors further comprise a plurality of coupling control systems each configured to tune the coupling value of a corresponding coupling device in the plurality of coupling devices to a coupling. Such quantum processors further comprise a set of readout devices each configured to measure the information from a corresponding quantum device in the plurality of quantum devices.Type: GrantFiled: March 4, 2009Date of Patent: August 30, 2011Assignee: D-Wave Systems Inc.Inventors: Alexander Maassen van den Brink, Peter Love, Mohammad H. S. Amin, Geordie Rose, David Grant, Miles F. H. Steininger, Paul Bunyk, Andrew J. Berkley