Patents by Inventor Peter M. Pani

Peter M. Pani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7876126
    Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 25, 2011
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7863932
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: January 4, 2011
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20100327907
    Abstract: In one embodiment, an integrated circuit has an L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors and (L+2) levels of conductors for L at least equal to one. An (i?1)-th level of conductors comprising Ii?1 number of conductors selectively couple to the i-th level of conductors comprising Ii number of conductors which comprise of D[i] sets of conductors in the L-PSN, where i is selected from [1:L+1], through ((Ii?1×D[i])+Ii×Q) number of switches where each conductor of the Ii?1 number of conductors selectively couples to at least (D[i]+Q) number of conductors of the Ii number of conductors, at least one conductor from each of the D[i] sets of conductors, for Q at least equal to one and D[i] greater than one. The integrated circuit can be used in various electronic devices.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Inventors: Benjamin S. Ting, Peter M. Pani
  • Patent number: 7830173
    Abstract: An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: November 9, 2010
    Assignee: Actel Corporation
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20100244895
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Application
    Filed: June 4, 2010
    Publication date: September 30, 2010
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7777519
    Abstract: In one embodiment, an integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: August 17, 2010
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7768302
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: August 3, 2010
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20100156461
    Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Application
    Filed: March 9, 2010
    Publication date: June 24, 2010
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20100141298
    Abstract: In one embodiment, an integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Application
    Filed: February 10, 2010
    Publication date: June 10, 2010
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20100134143
    Abstract: In one embodiment, an integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Application
    Filed: December 3, 2008
    Publication date: June 3, 2010
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7714611
    Abstract: In one embodiment, an integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: May 11, 2010
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7705629
    Abstract: In one embodiment, the integrated circuit has a L-level permutable switching network (L-PSN) comprising L levels of intermediate conductors. The integrated circuit can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: April 27, 2010
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20090273368
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Application
    Filed: May 26, 2009
    Publication date: November 5, 2009
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20090174431
    Abstract: An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
    Type: Application
    Filed: March 10, 2009
    Publication date: July 9, 2009
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7557613
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: July 7, 2009
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7460529
    Abstract: An interconnection fabric using switching networks hierarchically to allow interconnections of large number of a first plurality of conductors to a large number of k plurality of conductors is described. The resulting interconnection fabric can be used in switching networks, routers and programmable logic circuits.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: December 2, 2008
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20080272806
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Application
    Filed: July 16, 2008
    Publication date: November 6, 2008
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Patent number: 7423453
    Abstract: Efficient layout schemes to implement switching networks of an interconnection fabric in an integrated circuit to connect two sets of conductors through rows of switches with prescribed number of tracks over the switching area are described. The layout schemes can be used repeatedly for multiple-stage switching network and/or hierarchically arranged switching networks.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: September 9, 2008
    Assignee: Advantage Logic, Inc.
    Inventors: Benjamin S. Ting, Peter M. Pani
  • Patent number: 7417457
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect, through a second set of switches, to a third plurality of sets of conductors. Each conductor of a set of the third plurality sets of conductors either connects, physically, to one pin in each of a plurality of functional blocks or, through a third set of switches, to a subsequent fourth set of conductors. The SN is scalable for larger sets of conductors by adding additional sets of intermediate conductors in a hierarchically fashion.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: August 26, 2008
    Assignee: Advantage Logic, Inc.
    Inventors: Peter M. Pani, Benjamin S. Ting
  • Publication number: 20080191739
    Abstract: An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
    Type: Application
    Filed: April 15, 2008
    Publication date: August 14, 2008
    Inventors: Peter M. Pani, Benjamin S. Ting