Abstract: A phase locked loop (PLL) lock detector may be configured to observe the phase error signal from a phase comparator of a PLL circuit. The PLL lock detector may accumulate a sum of phase errors and compare the sum of phase errors to determine whether the PLL circuit is locked in phase with the reference signal. Various modifications to the phase error signal and sum of phase errors may be used to improve the efficiency of the PLL lock detector. Configurable settings for the accumulator and a comparator may be used to adjust the operation of the PLL lock detector.

Abstract: A mechanism can be implemented in a communication unit of a network device to utilize periods of silence encountered in voice communication to conserve power at the network device. In some embodiments, it can be determined that one or more packets of a received RF signal comprise audio data. The communication unit of the network device can determine whether the audio data associated with the one or more packets comprises voice information. The network device can switch to a power save mode based, at least in part, on determining that the audio data associated with the one or more packets does not comprise voice information.

Abstract: A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state.

Abstract: A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

Abstract: A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

Abstract: A tri-state control mechanism can be implemented for a line driver of a transmitter unit to switch the output impedance of the transmitter unit between a low impedance state in the transmit mode and a high impedance state in the receive mode while minimizing turn-off glitch. It may be determined whether a communication device comprising the transmitter unit is configured in a transmit operating mode or a receive operating mode. If the communication device is configured in the receive operating mode, a first bias voltage can be generated to bias output transistors of the line driver circuit in a sub-threshold state. If the communication device is configured in the transmit operating mode, a second bias voltage can be generated to bias output transistors of the line driver circuit in a saturation state.

Abstract: A mechanism can be implemented in a communication unit of a network device to utilize periods of silence encountered in voice communication to conserve power at the network device. In some embodiments, it can be determined that one or more packets of a received RF signal comprise audio data. The communication unit of the network device can determine whether the audio data associated with the one or more packets comprises voice information. The network device can switch to a power save mode based, at least in part, on determining that the audio data associated with the one or more packets does not comprise voice information.

Abstract: Microfluidic structures featuring substantially circular channels may be fabricated by embossing polymer sheets.

Abstract: Methods of fabricating microfluidic structures featuring substantially circular channels are provided. The methods involve (a) providing a patterned wafer comprising at least one exposed electrically conductive region and at least one exposed electrically insulating region; (b) electroplating an inverse channel portion with substantially semicircular cross section onto the wafer, thereby forming a first master mold; (c) employing the first master mold so as to emboss a channel portion in a first polymer sheet; and (d) aligning and bonding the first polymer sheet with a second polymer sheet having a corresponding channel portion such as to define a first channel with substantially circular cross section between the polymer sheets.

Abstract: A low drop out voltage regulator (LDO) is capable of operating in one of two different modes based on externally connected components. In one mode, the LDO directly generates a regulated output voltage. In a second mode, the LDO drives an external PNP transistor to generate a regulated output voltage. In both modes, a relatively large bypass capacitor may be connected to the output voltage node to bypass high-frequency loading on the output voltage node. However, the bypass capacitor creates a low frequency pole in the frequency response of the LDO, which can diminish phase margin and reduce overall stability. An on chip compensation network beneficially counteracts the low frequency pole with an appropriately placed zero, thereby resulting in improved phase margin and greater stability.

Abstract: In one embodiment, a high-throughput flow system includes an array of wells and a separate mechanical tip positioned within each well. Each mechanical tip is separately actuated to impart a shear stress pattern.

Abstract: A compact constant current generator that can operate with a positive supply voltage of 1.22 V (or lower) and minimize noise is provided. The constant current generator can include a bandgap reference circuit and a single gain stage. Notably, the bandgap reference circuit can advantageously generate differential node voltages. The gain stage can amplify those differential node voltages and generate a constant current having a temperature coefficient substantially equal to zero. Advantageously, this single gain stage can minimize the number of components, thereby resulting in a compact and efficient current generator.

Abstract: Microfluidic structures featuring substantially circular channels may be fabricated by embossing polymer sheets.

Abstract: A phase selector for selecting a differential output is provided. The phase selector can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the transistor circuits can be used to dump an output current generated by the first differential input signal to Vdd. The other transistor circuit can be used to steer an output current generated by the second differential input signal to two output lines, thereby providing a differential output signal on the output lines.

Abstract: The invention relates to a roof structure for a vehicle with a roof panel (1), with side wall panels (2) and with a front and rear roof frame (10, 11), the roof panel (1) having a front side (3) and a rear side (4) and a longitudinal side (5, 6) on both sides, and the front roof frame (10) being assigned to the front side (3) of the roof panel (1) and the rear roof frame (11) being assigned to the rear side (4). The roof panel (1) is connected at least indirectly at its longitudinal sides (5, 6) to the side wall panels (2). The roof panel (1) is connected to the side wall panel (2) and/or to the front roof frame (10) and/or to the rear roof frame (11) via an angled bar (20). The invention likewise relates to a method for producing the roof structure.

Abstract: The invention relates to a roof structure for a vehicle with a roof panel (1), with side wall panels (2) and with a front and rear roof frame (10, 11), the roof panel (1) having a front side (3) and a rear side (4) and a longitudinal side (5, 6) on both sides, and the front roof frame (10) being assigned to the front side (3) of the roof panel (1) and the rear roof frame (11) being assigned to the rear side (4). The roof panel (1) is connected at least indirectly at its longitudinal sides (5, 6) to the side wall panels (2). The roof panel (1) is connected to the side wall panel (2) and/or to the front roof frame (10) and/or to the rear roof frame (11) via an angled bar (20). The invention likewise relates to a method for producing the roof structure.

Abstract: A single-chip CMOS direct conversion transceiver includes an RF circuit, a transmitter having a synthesizer, a receiver having a baseband filter, and a demodulator. The synthesizer is coupled to the RF circuit. The baseband filter is coupled to the RF circuit and the synthesizer. The demodulator is coupled to the baseband filter. The RF circuit, the synthesizer, the baseband filter, and the demodulator are arranged and configured in CMOS devices and provide a complete interface between an antenna and a voiceband codec.

Abstract: The invention relates to a method for the production of a side wall module for the bodywork of a motor vehicle, having a panel which leaves open a side wall part. In this case, a side wall structure, which extends to the rear in the longitudinal direction of the vehicle at least from an A-pillar as far as a rear wheel mounting and comprises an inner part and a wall part integrally reinforcing the side wall module, is joined in the transverse direction of the vehicle to a side wall panel which has previously been deep drawn from a blank and cut, with window openings and at least one door opening being formed. The wall part is fastened on the outside of the inner part of the side wall structure.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.