Abstract: There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Abstract: There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Abstract: There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.

Abstract: The invention relates to a design system of logic products, which includes a time-consuming detailed simulation part and a fast whole-product simulation part. Two new parameters Ac and n are added to a delay library of the fast whole-product simulation part for the purpose of hot carrier degradation calculations (Degradation=Actn) (wherein n is a slope of time dependence and depends on a bias voltage that the circuit configuration and cells receive, and Ac depends on the bias voltage that the circuit configuration and cells receive). Thereby, it is feasible to carry out optimization of the design by a fast whole-product simulation part without crossing the time-consuming detailed simulation part.

Abstract: The invention relates to a design system of logic products, which includes a time-consuming detailed simulation part and a fast whole-product simulation part. Two new parameters Ac and n are added to a delay library of the fast whole-product simulation part for the purpose of hot carrier degradation calculations (Degradation=Actn) (wherein n is a slope of time dependence and depends on a bias voltage that the circuit configuration and cells receive, and Ac depends on the bias voltage that the circuit configuration and cells receive). Thereby, it is feasible to carry out optimization of the design by a fast whole-product simulation part without crossing the time-consuming detailed simulation part.

Abstract: The invention relates to a design system of logic products, which includes a time-consuming detailed simulation part and a fast whole-product simulation part. Two new parameters Ac and n are added to a delay library of the fast whole-product simulation part for the purpose of hot carrier degradation calculations (Degradation=Actn) (wherein n is a slope of time dependence and depends on a bias voltage that the circuit configuration and cells receive, and Ac depends on the bias voltage that the circuit configuration and cells receive). Thereby, it is feasible to carry out optimization of the design by a fast whole-product simulation part without crossing the time-consuming detailed simulation part.