SIMULATION METHOD AND SIMULATION PROGRAM
There is a need for keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated. This simulation method includes a first process and a second process. The first process saves result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies. The second process uses result data saved by the first process to reproduce internal node data not saved by the first process. Result data for the interface node between hierarchies indirectly determines a value for the internal node. Result data to be saved is data concerning the interface node between hierarchies. The amount of saved data and the time needed for the second process are independent of a hierarchical level or a higher-level or lower-level hierarchy.
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The present application claims priority from Japanese patent application No. 2006-31868 filed on Feb. 9, 2006, the content of which is hereby incorporated by reference into this application.
BACKGROUND OF THE INVENTIONThe present invention relates to a data processing method typified by a circuit simulating method and a simulation program. For example, the invention relates to a technology effectively applied to a simulator used for development or design of semiconductor integrated circuits.
The circuit simulation technology is used as a circuit verification technology for the circuit design and the layout design of a semiconductor integrated circuit. Recently, devices have become smaller and consequently circuits have become large in scale and highly integrated. It becomes obvious that the circuit simulation time becomes long and the amount of data for saving simulation results increases. When a designer wants to ensure he obtains the information he needs, he needs to specify explicitly the information to output before doing the actual circuit simulation. Only specified information is saved as result data. Accordingly, result data that is not saved cannot be displayed. To enable any result to be displayed without specifically selecting the data to output, it is necessary to perform a simulation that specifies all the circuit nodes to be output. As a result, the data of from all nodes need to be maintained. A large-scale circuit generates a large amount of data because all the results need to be saved. It is practically impossible to save all the data. Increasing the amount of data for result display also increases the retrieval time for result data and slows display speed. In addition, large-scale circuits increase simulation process time and therefore also increases the re-simulation time required when the circuit is partially modified or an element parameter is modified.
Concerning reduction of a storage area for saving simulation results, Japanese Unexamined Patent Publication No. Hei 11(1999)-96207 describes a technology of compressing the saved simulation result data. Japanese Unexamined Patent Publication NO. Hei 9(1997)-259151 discloses a technology that divides a circuit from an upstream and a downstream side of a signal path with respect to a modified circuit block and performs simulation for each part downstream of the modified block which would be affected by the modification of the block.
However, the technology described in Japanese Unexamined Patent Publication No. Hei 11(1999)-96207 additionally requires compression and decompression processes and further increases computation time due to the simulation and the result display. The technology described in Japanese Unexamined Patent Publication NO. Hei 9(1997)-259151 decreases the amount of memory used for computation, but does not decrease the storage capacity of auxiliary storage means for maintaining results. The circuit needs to be divided so as not to be dependant on the other simulation results and needs to be serially simulated. The process time is considered to increase.
The applicants made an application for patent (International Publication 03/036523 in the form of a brochure). The simulation method according to the application includes first and second processes. The first process performs simulation and saves a result so that a result output node corresponds to a higher hierarchical circuit node for hierarchical circuit data. The second process performs simulation under a specified initial condition for a lower hierarchical circuit node using the simulation result saved by the above-mentioned process as input/output information about a circuit area containing the lower hierarchical circuit node.
SUMMARY OF THE INVENTIONThe inventors further examined the applied invention. The first point is trade-off between the amount of data to be saved and the simulation speed. The second point is generation of voltage source loops during simulation. According to the first point, deepening the lower-level hierarchy below which no results data are saved would increase the amount of data to be saved but shortens the simulation time for lower-level hierarchies. An attempt to decrease the amount of data to be saved adversely increases the simulation time for lower-level hierarchies. With respect to the second point, the simulation may include a path that connects with at least only one of voltage sources and an inductor. When a loop is formed by connecting the voltage source or the ground to both ends of the path, the loop will cause a situation where inconsistencies in the voltage may occur, and the current through the loop cannot be calculated. A loop formed only by voltage sources and the inductors is called a voltage source loop. No simulation result may be obtained when a voltage source loop is generated in a circuit under simulation.
It is an object of the present invention to provide a simulation method capable of displaying data at any result output point without saving all simulation result data for a large-scale object under simulation and capable of keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated.
It is another object of the present invention to provide a simulation method capable of displaying data at any result output point without saving all simulation result data for a large-scale object under simulation while not forming any voltage source loops in the process.
These and other objects and novel features of the invention may be readily ascertained by referring to the following description and appended drawings.
The following describes an overview of representative means of the invention disclosed in this application.
[1]<1-A> A simulation method according to the invention includes: a first process for saving result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies; and a second process for using result data saved by the first process to reproduce internal node data not saved by the first process. A specified initial condition is preferably equivalent to that for the simulation of the first process. It is only necessary to allow the first process to save the initial condition along with a simulation result and make the initial condition reusable. In this manner, a simulation result is saved only to result data for an interface node between hierarchies. It is possible to decrease the amount of result data to be saved for simulation. No simulation result is saved for an internal node other than the interface node. Under the same initial condition as the simulation condition for the first process, result data for the interface node between hierarchies indirectly determines a value for the internal node. When the request to display output data happens to select an interface node for which data is already available from the first process, it is only necessary to display the result of the simulation of the first process in the second process. Even though the amount of stored data is small (the results data from the first process), it is possible to display all data in the circuit as if all the data had been saved for a large-scale simulation object such as a large-scale integrated circuit. Decreasing the amount of result data to be saved can shorten the time for retrieving result data. Since the scale of a targeted circuit can be decreased during simulation by the second process, it is possible to shorten the re-simulation time when making a partial circuit modification or an element parameter modification to a large-scale circuit. Result data to be saved is data concerning the interface node between hierarchies. The data is independent of the hierarchical level; interface nodes are saved at any specified hierarchical level or all hierarchical levels. Accordingly, it is possible to keep the amount of data to be saved and the simulation process time almost constant irrespectively of the hierarchical level of a hierarchical circuit to be simulated.
Preferably, the first process also saves simulation result data of an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value of a voltage source or a current source in another hierarchy (these voltage and current sources are called dependent voltage sources and dependent current sources, since they are dependent on another quantity). Preferably, the first process saves simulation result data for an element in the hierarchy when the simulation result data determines a value for a voltage source or current source in another hierarchy (
<1-B> At this time, a hierarchical circuit area (3p) having an internal node as an object of the second process is supposed to have a partial circuit (VLC) including one of elements such as a voltage source (Vs) and an inductor (Lt) or at least two connected elements such as the voltage source and the inductor. The hierarchical circuit area is supposed to have one or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, e.g., one or more specific nodes (N1 through NN) as interface nodes for connection to a higher-level hierarchical circuit. Alternatively, the hierarchical circuit area is supposed to have one or more specific nodes (M1 through MN) as interface nodes for connection to a lower-level hierarchical circuit. The partial circuit is supposed to be connected to a ground potential (GND). The second process then supplies electric current information (IN1 through INN and IM1 through IMN) as input/output information to the specific node (
A hierarchical circuit area having an internal node of which the output result is desired in the second process may have a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit (CIR) for connection to the partial circuit. The one or more specific nodes as interface nodes include, for example, those (N1 through NN) connected to a higher-level hierarchical circuit or those (M1 through MN) connected to a lower-level hierarchical circuit. The partial circuit is connected to a ground potential. The second process then supplies electric current information as input/output information to all specific nodes for the partial circuit (VLCv) (
A hierarchical circuit having an internal node as an object of the second process may have a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit. The one or more specific nodes as interface nodes include, for example, those (N1 through NN) connected to a higher-level hierarchical circuit or those (M1 through MN) connected to a lower-level hierarchical circuit. The partial circuit is connected to a ground potential. If the case is such that in the second process electric current flowing through voltage sources of the partial circuit are not required, then all the specific nodes are floated (
A hierarchical circuit area having an internal node as an object of the second process may have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy. The one or more specific nodes as interface nodes include, for example, those (N1 through NN) connected to a higher-level hierarchical circuit or those (M1 through MN) connected to a lower-level hierarchical circuit. The partial circuit is connected to a ground potential. If in the second process extracting the electric current flowing through the elements is not necessary, the partial circuit is then deleted (
<1-C> According to the above-mentioned description, the partial circuit is connected to the ground potential. However, this is not mandatory. A hierarchical circuit having an internal node as an object of the second process may have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy. The two or more specific nodes as interface nodes include, for example, those (N1 through NN) connected to a higher-level hierarchical circuit or those (M1 through MN) connected to a lower-level hierarchical circuit. The partial circuit is not connected to a ground potential. The second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes (
Similarly, a hierarchical circuit area having an internal node as an object of the second process may have a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit. The two or more specific nodes as interface nodes include, for example, those (N1 through NN) connected to a higher-level hierarchical circuit or those (M1 through MN) connected to a lower-level hierarchical circuit. The partial circuit is not connected to a ground potential. The second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes (
Similarly, a hierarchical circuit having an internal node as an object of the second process may have a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit. The two or more specific nodes as interface nodes include, for example, those (N1 through NN) connected to a higher-level hierarchical circuit or those (M1 through MN) connected to a lower-level hierarchical circuit. The partial circuit is not connected to a ground potential. If the electric current information flowing through the voltage sources of the partial circuit is not desired in the second process, voltage source information as input/output information to one specific node is adequate, and the remaining specific nodes can be floated (
A hierarchical circuit area having an internal node as an object of the second process may have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes as interface nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy. The one or more specific nodes as interface nodes include, for example, those (N1 through NN) connected to a higher-level hierarchical circuit or those (M1 through MN) connected to a lower-level hierarchical circuit. The partial circuit is not connected to a ground potential. If in the second process electric current flowing through all elements of the partial circuit can be ignored, then the partial circuit can be deleted.
[2] A simulation method according to another aspect of the invention includes: an extraction process for extracting a circuit node in a specified hierarchy from hierarchical circuit data; a simulation execution process for executing a circuit simulation using a circuit node extracted by the extraction process as a result output node. The method further includes: a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; and a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy.
Similar to <1-A> as mentioned above, the simulation re-execution process can keep the amount of data to be saved and the simulation process time almost constant irrespectively of the hierarchical level of a hierarchical circuit to be simulated. It is possible to perform the hierarchical simulation according to the above-mentioned method with shortened simulation time. As described in <1-B> and <1-C>, it is possible to provide the simulation method including processes concerning a partial circuit so as to prevent voltage source loops to be formed.
An embodiment of the invention may further include a display process for displaying result data saved by the save process in response to an instruction to display a simulation result or displaying a simulation result obtained by the simulation re-execution process.
For example, the extraction process registers a circuit node identifiable at a specified hierarchical level each time the extraction process changes a hierarchical level to a lower one while keeping track of a series of references to a lower-level hierarchy in hierarchical circuit data. This process may be performed for all series of references in an object under simulation. This makes it possible to extract a result output node for the simulation by specifying a hierarchy.
[3] With respect to the display process for the simulation result, a simulation method according to an embodiment includes: a simulation execution process for performing a circuit simulation using a circuit node for a hierarchical circuit data in a specified hierarchy as a result output node; a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; and a first display process for displaying result data retrieved from those saved by the save process as a result of the simulation execution process. The method further includes: a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy; and a second display process for displaying result data from the simulation re-execution process.
Similarly to <1-A> as mentioned above, the simulation re-execution process can keep the amount of data to be saved and the simulation process time almost constant irrespectively of the hierarchical level of a hierarchical circuit to be simulated. It is possible to perform the hierarchical simulation according to the above-mentioned method shortening the simulation time. As described in <1-B> and <1-C>, it is possible to provide the simulation method including processes concerning a partial circuit so as to prevent voltage loops from forming.
[4] A simulation method according to still another aspect of the invention includes: a simulation execution process for performing a circuit simulation using hierarchical circuit data for a specified hierarchy; and a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies. The method further includes a simulation re-execution process for performing a circuit simulation for a circuit node reflecting modification of the hierarchical circuit data, when modified, using the saved result data concerning an interface node between the circuit node and an interfaced hierarchy one level higher or lower. In this manner, the method eliminates the need for redoing overall simulation and helps shorten the simulation time. The method can shorten the simulation time similarly to <1-A> and prevent the formation of a voltage source loop similarly to <1-B> and <1-C>.
[5] A simulation method according to an embodiment considering device simulation based on calculating values at mesh or grid points other than the circuit simulation includes: a first process for extracting a result output point in a specified higher-level hierarchy from an object under simulation; a second process for simulating an extracted result output point; and a third process for saving result data that is obtained by the simulation execution process for a result output grid or mesh node and relates to an interface node between higher-level and lower-level hierarchies. The method further includes a fourth process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and simulating a device mesh or grid node in the specified hierarchy so as to obtain simulation result data under a condition equivalent to that for a simulation by the second process.
[6] A simulation program according to the invention is executed by a computer so as to perform a data process for supporting circuit simulation. The data process includes: a first process for saving result data obtained from simulating an interface node between higher-level and lower-level hierarchies in accordance with a result of simulation using hierarchical circuit data hierarchized for multiple hierarchies; and a second process for using result data saved by the first process to reproduce internal node data not saved by the first process. A simulation program can easily embody the simulation method.
A simulation program according to another embodiment provides a computer-based data process including: an extraction process for extracting a circuit node in a specified hierarchy from hierarchical circuit data; a simulation execution process for executing a circuit simulation using a circuit node extracted by the extraction process as a result output node; a save process for saving result data that relates to an interface node between higher-level and lower-level hierarchies and is obtained by the simulation execution process for a result output node; and a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy.
A simulation program according to still another embodiment provides a computer-based data process including: a simulation execution process for performing a circuit simulation using a circuit node for a hierarchical circuit data in a specified hierarchy as a result output node; a save process for saving result data that relates to an interface node between higher-level and lower-level hierarchies and is obtained by the simulation execution process for a result output node; and a first display process for displaying result data retrieved from those saved by the save process as a result of the simulation execution process; a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy; and a second display process for displaying result data from the simulation re-execution process.
A simulation program according to yet another embodiment provides a computer-based data process including: a first process for extracting a result output point in a specified higher-level hierarchy from an object under simulation; a second process for simulating an extracted result output point; a third process for saving result data that relates to an interface node between higher-level and lower-level hierarchies and is obtained by the simulation execution process for a result output node; and a fourth process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and simulating a circuit node in the specified hierarchy so as to obtain simulation result data under a condition equivalent to that for a simulation by the second process.
The following summarizes effects provided by the representative aspects of the invention disclosed in this application.
It is possible to provide a simulation method capable of displaying data at any result output point without saving all simulation result data for a large-scale object under simulation and capable of keeping the amount of data to be saved and a simulation process time almost constant irrespectively of a hierarchical level of a hierarchical circuit to be simulated.
In
As clearly understood from
After the saved result data 4 is obtained, a partial circuit modification or an element parameter modification may be made to the circuit under simulation 1. The following describes the method of obtaining a simulation result reflecting the modification.
A technique similar to the on-the-fly simulation can be used to simulate the circuit area 6 that is influenced by the partial circuit modification or the like. Accordingly, the scale of a circuit to be simulated can be reduced. It is possible to shorten the re-simulation time for making a partial circuit modification or an element parameter modification to a large-scale circuit.
The following describes a case of using data for an internal node or an element as result saving data. According to an example in
The simulation method described with reference to
When supplied with display node specification information 16, simulation result display control means 17 retrieves whether or not the saved result data 4 contains the circuit node specified by the information. When the specified circuit node is contained, the result display control means 17 controls a display 19 to display data for the retrieved circuit node as result waveform information 18.
When the saved result data 4 does not contain data for the circuit node specified by the display node specification information 16, the on-the-fly simulation is performed and the display 19 displays waveform information about the necessary circuit node. This process is controlled by partial circuit simulation control means 20 that controls the on-the-fly simulation and the like. When the saved result data 4 does not contain data for the specified circuit node, a re-execution control unit 24 allows the means to create control input data for partial re-execution 21 to generate information needed for the circuit simulation that uses the circuit node as a result output node. To do this, the re-execution control unit 24 references the netlist 13, the control information 14, the device characteristics information 15, and the saved result data 4. Generated control circuit simulator input data for partial re-execution 22 includes, for example, saved information for the nodes N5 through N8 for partially simulating the circuit area 3a in
The following describes a process for extracting a result output node whose data is to be saved. This process corresponds to the result output node extraction process at Step S2 in
The following describes modes of the circuit block. The circuit block modes include: a mode containing only lower-level blocks as shown in
When the reference to a lower-level block becomes unavailable, the process determines whether or not the specified hierarchy level is equal to “1” (S26). Otherwise, the process returns to one block higher than the specified hierarchy level and decrements the specified hierarchy level by one (S27). For the block at the specified hierarchy level, the process determines whether or not the reference to all lower-level blocks have been covered (S28). That is, the process determines whether or not there is another lower-level block reference to be linked to the lower level. When there is another lower-level block reference as a result of the determination, the process moves to a lower-level block corresponding to the next lower-level block reference and increments the specified hierarchy level by one (S29). The process then returns to Step S21 and repeats the succeeding steps. When it is determined at Step S28 that there is not another lower-level block reference to be linked to the lower level from that specified hierarchy level, the process determines whether or not the specified hierarchy level is equal to “1” (S30). Otherwise, the process returns to Step S27. The process is repeated until the specified hierarchy level is determined to be “1” at Step S26 or S30. Finally, the process retrieves states of lower-level internal nodes and elements referenced by dependent voltage sources or current sources over all the hierarchy levels. The process adds a retrieved node to the result output node and registers the state of a retrieved element as the element information (S31).
According to the above-mentioned description, the extraction function of the result output node is provided as part of functions of the circuit simulator 10 in
<Preventing a Voltage Source Loop>
A method of previously preventing the on-the-fly simulation from generating a voltage source loop will be described. Referring now to
A second example will be described. As shown in
A third example will be described. A condition is that the partial circuit VLC includes one of the elements such as voltage source Vs and inductor Lt or at least two connected elements such as voltage source Vs and inductor Lt. Another condition is that there are provided one or more higher-level interface nodes N1 through NN externally connected with the partial circuit VLC. Still another condition is that the partial circuit VLC is connected to the ground potential GND. Yet another condition is that the on-the-fly simulation for the circuit area 3p eliminates consideration for electric currents flowing through all elements in the partial circuit VLC. Under these conditions, it is only necessary to perform the on-the-fly simulation by removing the partial circuit VLC as shown in
A fourth example will be described. According to the above-mentioned description, the partial circuit VLC is connected to the ground potential GND. This is not mandatory. Let us assume a circuit in
A fifth example will be described. According to the above-mentioned description, the partial circuit VLCv is connected to the ground potential GND. This is not mandatory. Let us assume a circuit in
A sixth example will be described. A condition is that the partial circuit VLC is not connected to the ground potential GND as shown in
With reference to
A second example will be described. As shown in
A third example will be described. As shown in
A fourth example will be described. According to the above-mentioned description, the partial circuit VLC is connected to the ground potential GND. This is not mandatory. Let us assume a circuit in
A fifth example will be described. According to the above-mentioned description, the partial circuit VLCv is connected to the ground potential GND. This is not mandatory. Let us assume a circuit in
A sixth example will be described. A condition is that the partial circuit VLC is not connected to the ground potential GND as shown in
The above-mentioned simulation method can display data at any result output points without saving all simulation result data concerning a large-scale object under simulation. The method is hardly subject to disadvantages due to a voltage source loop. Especially, the method saves result data concerning an interface node between higher-level and lower-level hierarchies. There may be a case of discarding all result data at hierarchies lower than a specified hierarchical level. Compared to such case, the method can keep the amount of data to be saved and the simulation process time almost constant irrespectively of the hierarchical level of a hierarchical circuit to be simulated.
The method requires a small storage capacity to be able to provide the data display performance equivalent to that for saving all simulation result data for a large-scale simulation object such as a large-scale integrated circuit. The method is hardly subject to disadvantages due to a voltage source loop.
The method can easily increase the speed to display simulation result data for a large-scale simulation object such as a large-scale integrated circuit. The method is hardly subject to disadvantages due to a voltage source loop.
While there has been described the invention made by the inventors based on the specific embodiments, it is to be distinctly understood that the invention is not limited thereto but may be otherwise variously embodied within the spirit and scope of the invention.
For example, a circuit under simulation may be scaled to include hundreds of thousands to millions of gates. According to the above-mentioned description, the on-the-fly simulation is positioned as an enhanced function of displaying a simulation result. Obviously, it is possible to understand the invention as partial simulation apart from the display. When the invention is positioned as an enhanced display function, the invention is not limited to the display of simulation results but can be understood from a viewpoint of displaying data as a result of processing hierarchical information.
It is to be distinctly understood that the simulation method can be interpreted as a simulation program using a computer for implementing functions or procedures as shown in the flowcharts. Provision of such simulation program can easily embody the simulation method.
The simulation method according to the invention can be applied to not only circuit simulation, but also to device simulation. For example, device simulation may be performed by dividing a sectional area of a device such as a MOS transistor into meshed blocks and hierarchically comprehending them for simulation. In such case, the result output point corresponds to a focused point of electric current or voltage on the device section, for example. When the higher-level hierarchy is simulated, a result output point is found at a boundary of the mesh. When the lower-level hierarchy is simulated, a result output point is found in the mesh. There may be a need to obtain a result output point in the mesh as a simulation result. For this purpose, it is only necessary to perform a partial device simulation using an existing simulation result for an existing result output point at the mesh boundary and using the same initial simulation condition as that used for obtaining the existing result.
The invention can be widely applied to circuit simulation for semiconductor integrated circuits, device simulation for semiconductor devices, and the like.
Claims
1-11. (canceled)
12. A simulation method comprising:
- an extraction process for extracting a circuit node in a specified hierarchy from hierarchical circuit data;
- a simulation execution process for executing a circuit simulation using a circuit node extracted by the extraction process as a result output node;
- a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; and
- a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy.
13. The simulation method according to claim 12,
- wherein the save process saves simulation result data for an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value for a voltage source or current source in another hierarchy, and
- wherein the save process saves simulation result data for an element in the hierarchy when the simulation result data determines a value for a voltage source or current source in another hierarchy.
14. The simulation method according to claim 13,
- wherein the simulation re-execution process performs a simulation under a same initial condition as for a simulation by the simulation execution process.
15. The simulation method according to claim 14, further comprising:
- a display process for displaying result data saved by the save process in response to an instruction to display a simulation result or displaying a simulation result obtained by the simulation re-execution process.
16. The simulation method according to claim 15,
- wherein the extraction process registers a circuit node identifiable at a specified hierarchical level each time the extraction process changes a hierarchical level to a lower one while keeping track of a series of reference to a lower-level hierarchy in hierarchical circuit data, and
- wherein this process is performed for all series of reference in an object under simulation.
17. A simulation method comprising:
- a simulation execution process for performing a circuit simulation using a circuit node for a hierarchical circuit data in a specified hierarchy as a result output node;
- a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies;
- a first display process for displaying result data retrieved from those saved by the save process as a result of the simulation execution process;
- a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy; and
- a second display process for displaying result data from the simulation re-execution process.
18. The simulation method according to claim 17,
- wherein the save process saves simulation result data for an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value for a voltage source or current source in another hierarchy, and
- wherein the save process saves simulation result data for an element in the hierarchy when the simulation result data determines a value for a voltage source or current source in another hierarchy.
19. The simulation method according to claim 18,
- wherein the simulation re-execution process performs a simulation under an initial condition equivalent to that for a simulation by the simulation execution process.
20. A simulation method comprising:
- a simulation execution process for performing a circuit simulation using a circuit node for a hierarchical circuit data in a specified hierarchy as a result output node;
- a save process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; and
- a simulation re-execution process for performing a circuit simulation for a circuit node reflecting modification of the hierarchical circuit data, when modified, using the saved result data concerning an interface node between the circuit node and an interfaced hierarchy one level higher or lower.
21. The simulation method according to claim 20,
- wherein the simulation re-execution process parallel performs a circuit simulation for the modification reflecting circuit nodes whose signal paths are independent of each other.
22. A simulation method comprising:
- a first process for extracting a result output point in a specified higher-level hierarchy from an object under simulation;
- a second process for simulating an extracted result output point;
- a third process for saving result data that is obtained by the simulation execution process for a result output node and relates to an interface node between higher-level and lower-level hierarchies; and
- a fourth process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and simulating a circuit node in the specified hierarchy so as to obtain simulation result data under an initial condition equivalent to that for a simulation by the second process.
23. The simulation method according to claim 22,
- wherein the save process saves simulation result data for an internal node different from an interface node between higher-level and lower-level hierarchies when the simulation result data determines a value for a voltage source or current source in another hierarchy, and
- wherein the save process saves simulation result data for an element in the hierarchy when the simulation result data determines a value for a voltage source or current source in another hierarchy.
24. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be connected to a ground potential, and
- wherein the second process then supplies electric current information as input/output information to the specific node.
25. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be connected to a ground potential, and
- wherein the second process then supplies electric current information as input/output information to the specific node.
26. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, and
- wherein all the specific nodes are then floated.
27. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, and
- wherein the partial circuit is then deleted.
28. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be not connected to a ground potential, and
- wherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.
29. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be not connected to a ground potential, and
- wherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.
30. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be not connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, and
- wherein the second process then supplies voltage source information as input/output information to one specific node and floats the remaining specific nodes.
31. The simulation method according to claim 12,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be not connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, and
- wherein the partial circuit is then deleted.
32. (canceled)
33. A simulation program executed by a computer so as to perform a data process for supporting circuit simulation, the data process comprising:
- an extraction process for extracting a circuit node in a specified hierarchy from hierarchical circuit data;
- a simulation execution process for executing a circuit simulation using a circuit node extracted by the extraction process as a result output node;
- a save process for saving result data that relates to an interface node between higher-level and lower-level hierarchies and is obtained by the simulation execution process for a result output node; and
- a simulation re-execution process for using the saved result data concerning an interface node between a specified hierarchy and a hierarchy one level higher or lower and obtaining simulation result data for a circuit node in the specified hierarchy.
34-35. (canceled)
36. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be connected to a ground potential, and
- wherein the second process then supplies electric current information as input/output information to the specific node.
37. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be connected to a ground potential, and
- wherein the second process then supplies electric current information as input/output information to the specific node.
38. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be connected to a ground potential, and
- wherein the second process then supplies electric current information as input/output information to the specific node.
39. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be connected to a ground potential, and
- wherein the second process then supplies electric current information as input/output information to the specific node.
40. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, and
- wherein all the specific nodes are then floated.
41. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, and
- wherein all the specific nodes are then floated.
42. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, and
- wherein the partial circuit is then deleted.
43. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, and
- wherein the partial circuit is then deleted.
44. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be not connected to a ground potential, and
- wherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.
45. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be not connected to a ground potential, and
- wherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.
46. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be not connected to a ground potential, and
- wherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.
47. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or at least two connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be not connected to a ground potential, and
- wherein the second process then supplies voltage source information as input/output information to one of the two or more specific nodes and supplies current source information as input/output information to the remaining specific nodes.
48. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be not connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, and
- wherein the second process then supplies voltage source information as input/output information to one specific node and floats the remaining specific nodes.
49. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one voltage source or two or more connected voltage sources, two or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy, and another circuit for connection to the partial circuit,
- wherein the partial circuit is supposed to be not connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through a voltage source of the partial circuit, and
- wherein the second process then supplies voltage source information as input/output information to one specific node and floats the remaining specific nodes.
50. The simulation method according to claim 17,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be not connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, and
- wherein the partial circuit is then deleted.
51. The simulation method according to claim 20,
- wherein a hierarchical circuit having an internal node as an object of the second process is supposed to have a partial circuit including one of elements such as a voltage source and an inductor or at least two connected elements such as a voltage source and an inductor and have one or more specific nodes for connecting the partial circuit to a hierarchical circuit in another hierarchy,
- wherein the partial circuit is supposed to be not connected to a ground potential,
- wherein the second process is supposed to ignore an electric current flowing through all elements of the partial circuit, and
- wherein the partial circuit is then deleted.
Type: Application
Filed: Apr 2, 2010
Publication Date: Aug 5, 2010
Applicant:
Inventors: Peter Maurice LEE (Tokyo), Junji Sato (Tokyo), Goichi Yokomizo (Tokyo)
Application Number: 12/753,832
International Classification: G06F 17/50 (20060101);