Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A first set of parameters associated with operating an interface between a host system and a memory system may be determined based on a first training operation, where an indication of the first set of parameters and a first temperature associated with the first training operation may be stored. A second set of parameters associated with operating the interface may be determined based on a second training operation, where an indication of the second set of parameters and a second temperature associated with the second training operation may be stored. At a third temperature, a third set of parameters may be configured for operation of the interface based on the stored sets of parameters, and communications over the interface may be performed in accordance with the third set of parameters.

Abstract: Methods, systems, and devices for error control for fuse arrays are described. The described techniques may enable a memory system to perform error control on a fuse block. The fuse block may include one or more fuses that store error control information that is generated based on the control information stored in the corresponding fuse block. The memory system may therefore use the error control information to determine whether the fuse block contains an error and to correct one or more errors contained in the fuse block. In some examples, the memory system may output an error flag or update an error log when an error is detected. In some examples, each fuse block may include multiple sets of error control fuses, and a fuse selector may determine which set of error control fuses to use for error control of the fuse block.

Abstract: Methods, systems, and devices for multiple fuse comparison for early failure check are described. The method may include a memory system receiving signaling that indicates a first resistance level associated with one or more first fuses of a first set of fuses and receiving signaling that indicates a second resistance level associated with one or more second fuses of a second set of fuses that stores redundant data with respect to the first set of fuses. Further, the method may include generating an error flag associated with the fuse array based on a comparison of the first resistance level and the second resistance level.

Abstract: Disclosed is a building board construction with increased surface strength. More specifically, increased nail pull strength is achieved via the application of an external surface coating. The surface coating is ideally applied to a paper faced gypsum building board. In one possible embodiment, the coating is formed from a water soluble polymer.

Abstract: Methods, systems, and devices for redundancy techniques for multi-channel memory devices are described. A memory device may be configured with multiple channels (e.g., channel sets) that can be operated in different modes, such as a two-channel mode and a one-channel redundancy mode. In the two-channel mode, the memory device may be configured to access each of multiple memory arrays using a respective channel. In the one-channel redundancy mode, the memory device may be configured to access multiple memory arrays using a single channel which may otherwise be accessed using separate channels, and the memory device may store copies of data on the multiple memory arrays. For example, the memory device may store a first copy of data communicated via a channel in a first memory array and may store a second copy of the data communicated via the channel in a second memory array.

Abstract: Methods, systems, and devices for activate commands for memory preparation are described. A memory device may receive an activate command for a row of a memory bank in the memory device. The activate command may include an indicator that indicates a type of an access operation associated with the activate command. The memory device may perform, based on the type of the access operation, an operation to prepare the memory device for the access operation. The memory device may then receive an access command for the access operation after performing the operation to prepare the memory device for the access operation.

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: Methods, systems, and devices for memory operations that support configuring a channel, such as a command/address (C/A) channel, are described. A configuration of a C/A channel may be dynamically adapted based on power saving considerations, control information execution latency, or both. Configuring a C/A channel may include determining a quantity of pins, or a quantity of cycles, both for communicating control information over the C/A channel. The quantity of pins may be determined based on previous control information transmissions, characteristics of a memory device, or predicted control information transmissions, or any combination thereof in some cases. The determined quantity of pins, quantity of cycles, or both may be explicitly or implicitly indicated to other devices (e.g., that use the C/A channel).

Abstract: A method of producing hydrogen gas comprising: hydrolyzing sodium borohydride (NaBH4) with water at a temperature of from about 20 to about 75° C. in the presence of ammonium-zinc decavanadate hexadecahydrate ((NH4)2[Zn(H2O)6]2·V10O28·4H2O); and, capturing hydrogen gas evolved as a hydrolysis product.

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

Abstract: Methods, systems, and devices for activate commands for memory preparation are described. A memory device may receive an activate command for a row of a memory bank in the memory device. The activate command may include an indicator that indicates a type of an access operation associated with the activate command. The memory device may perform, based on the type of the access operation, an operation to prepare the memory device for the access operation. The memory device may then receive an access command for the access operation after performing the operation to prepare the memory device for the access operation.

Abstract: A gripping device for gripping, holding and guiding containers, in particular bottle-like containers. The gripping device including at least one gripper arm pair having a first gripper arm as well as an oppositely designed second gripper arm, wherein both gripper arms have a respective bearing bore via which they can be pivotably mounted, and a closing means (or opening means) for the gripper arm pair. With the objective of providing a reliable opening mechanism, the first gripper arm has a contour lever and the second gripper arm has a follower lever in operative engagement with one another and serving as opening means (or closing means) for the gripper arm pair.

Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds are configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device configures a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device tracks or counts errors in the data and determine whether the threshold has been satisfied. The memory device transmits (e.g., to the host device) an indication whether the threshold has been satisfied, and the system performs functions to correct the errors and/or prevent further errors. The memory device also identifies errors in received commands or identifies errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).

Abstract: Methods, systems, and devices for cyclic redundancy check (CRC) comparison for error detection are described. A host system may determine an error cause associated with writing data to or reading data from a memory system. For writing data, the host system may transmit data and a CRC value to the memory system. The memory system may calculate another CRC value and indicate an error and the calculated CRC value based on the received and calculated CRC values being different. The host system may compare the calculated CRC value and the originally transmitted CRC value to determine an error cause. For reading data, the host system may receive data and an associated CRC value from the memory system, calculate a CRC value using the received data, and determine an error cause based on a comparison of the received CRC value, the calculated CRC, and an expected CRC value.

Abstract: A method for controlling an adaptive motor vehicle headlight (AMVH), wherein a first data storage device (DSD) is assigned to the AMVH, which is designed to emit different segmented light distributions having a resolution of at least 2×12 and has light sources arranged in segments for this purpose, each segment including at least one LED light source.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: Methods, systems, and devices for controlled and mode-dependent heating of a memory device are described. In various examples, a memory device or an apparatus that includes a memory device may have circuitry configured to heat the memory device. The circuitry configured to heat the memory device may be activated, deactivated, or otherwise operated based on an indication of a temperature (e.g., of the memory device). In some examples, activating or otherwise operating the circuitry configured to heat the memory device may be based on an operating mode (e.g., of the memory device), which may be associated with certain access operations or operational states (e.g., of the memory device). Various operations or operating modes (e.g., of the memory device) may also be based on indications of a temperature (e.g., of the memory device).

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A first set of parameters associated with operating an interface between a host system and a memory system may be determined based on a first training operation, where an indication of the first set of parameters and a first temperature associated with the first training operation may be stored. A second set of parameters associated with operating the interface may be determined based on a second training operation, where an indication of the second set of parameters and a second temperature associated with the second training operation may be stored. At a third temperature, a third set of parameters may be configured for operation of the interface based on the stored sets of parameters, and communications over the interface may be performed in accordance with the third set of parameters.

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.