Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

Abstract: A solid state photomultiplier includes at least one microcell configured to generate an initial analog signal when exposed to optical photons. The solid state photomultiplier further includes a quench circuit electrically coupled with the at least one microcell. The quench circuit includes at least one quench resistor configured to exhibit a substantially constant temperature coefficient of resistance over a selected temperature range.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract: A solid state photomultiplier includes at least one microcell configured to generate an initial analog signal when exposed to optical photons. The solid state photomultiplier further includes a quench circuit electrically coupled with the at least one microcell. The quench circuit includes at least one quench resistor configured to exhibit a substantially constant temperature coefficient of resistance over a selected temperature range.

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract: Embodiments of a photodiode array are provided herein. In some embodiments, a photodiode array may include a semiconductor layer configured to convert photons into analog electrical signals; and a passive layer having a first surface and a second surface disposed opposite the first surface, wherein the semiconductor layer is coupled to the first surface, and wherein the passive layer is configured to have a signal receiving component coupled directly to the second surface of the passive layer.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The transient voltage suppression (TVS) device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer. The TVS device also includes a conductive path electrically coupled between the second layer and an electrical connection to a circuit external to the TVS device, the conductive path configured to permit controlling a turning on of the TVS device at less than a breakdown voltage of the TVS device.

Abstract: A method and an apparatus for detecting photons are disclosed. The apparatus includes a solid state photo multiplier device having a plurality of microcells that have a band gap greater than about 1.7 eV at 25° C. The solid state photo multiplier device further includes an integrated quenching device and a thin film coating associated with each of the microcells. The solid state photo multiplier device disclosed herein operates in a temperature range of about ?40° C. to about 275° C.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: A method of fabricating an overvoltage protection device and an over-voltage circuit protection device are provided. The over-voltage circuit protection device includes a plurality of transient voltage suppression (TVS) devices coupled in electrical parallel.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract: A power transistor assembly and method of operating the assembly are provided. The power transistor assembly includes integrated transient voltage suppression on a single semiconductor substrate and includes a transistor formed of a wide band gap material, the transistor including a gate terminal, a source terminal, and a drain terminal, the transistor further including a predetermined maximum allowable gate voltage value, and a transient voltage suppression (TVS) device formed of a wide band gap material, the TVS device formed with the transistor as a single semiconductor device, the TVS device electrically coupled to the transistor between at least one of the gate and source terminals and the drain and source terminals, the TVS device including a breakdown voltage limitation selected to be greater than the predetermined maximum allowable gate voltage value.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon (Si), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: A monolithically integrated semiconductor assembly is presented. The semiconductor assembly includes a substrate including silicon carbide (SiC), and gallium nitride (GaN) semiconductor device is fabricated on the substrate. The semiconductor assembly further includes at least one transient voltage suppressor (TVS) structure fabricated in or on the substrate, wherein the TVS structure is in electrical contact with the GaN semiconductor device. The TVS structure is configured to operate in a punch-through mode, an avalanche mode, or combinations thereof, when an applied voltage across the GaN semiconductor device is greater than a threshold voltage. Methods of making a monolithically integrated semiconductor assembly are also presented.

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The device includes a first layer of wide band gap semiconductor material formed of a first conductivity type material, a second layer of wide band gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer and comprising an ion implanted material structure between 0.1 micrometers (?m) and 22.0 ?m thick, the second layer operating using punch-through physics, and a third layer of wide band gap semiconductor material formed of the first conductivity type material over at least a portion of the second layer.

Abstract: A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The TVS assembly includes a semiconductor die in a mesa structure that includes a first layer of a first wide band gap semiconductor having a conductivity of a first polarity, a second layer of the first or a second wide band gap semiconductor having a conductivity of a second polarity coupled in electrical contact with the first layer wherein the second polarity is different than the first polarity. The TVS assembly also includes a third layer of the first, the second, or a third wide band gap semiconductor having a conductivity of the first polarity coupled in electrical contact with the second layer. The layer having a conductivity of the second polarity is lightly doped relative to the layers having a conductivity of the first polarity.

Abstract: A method of manufacturing a heterostructure device is provided that includes implantation of ions into a portion of a surface of a multi-layer structure. Iodine ions are implanted between a first region and a second region to form a third region. A charge is depleted from the two dimensional electron gas (2DEG) channel in the third region to form a reversibly electrically non-conductive pathway from the first region to the second region. On applying a voltage potential to a gate electrode proximate to the third region allows electrical current to flow from the first region to the second region.