Patents by Inventor Peter Michael Kogge
Peter Michael Kogge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6094715Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: July 25, 2000Assignee: International Business Machine CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5966528Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: October 12, 1999Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5878241Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: March 2, 1999Assignee: International Business MachineInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5870619Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: April 29, 1997Date of Patent: February 9, 1999Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5842031Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 6, 1995Date of Patent: November 24, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christoper Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson
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Patent number: 5828894Abstract: Array processors are made by assembling individual microcomputer elements into an array. Larger arrays are called massively parallel processors. Some can operate in SIMD, while others can operate in MIMD, or SIMD and MIMD in special configurations. In a SIMD array of processors, there is a need to partition the processors into groups related to the type of problem they contain. When the grouping is the result of a computation within the processing element, it is desirable that each processing element be capable of assigning itself to a group, or maybe several groups. This disclosure describes a means of assigning processing elements to groups as an array function conducted in parallel by all active processing elements in the array, and then using grouping to select certain processing elements for a computation that is unique to the group.Type: GrantFiled: September 30, 1996Date of Patent: October 27, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge
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Patent number: 5822608Abstract: Multiprocessor parallel computing systems and a byte serial SIMD processor parallel architecture is used for parallel array processing with a simplified architecture adaptable to chip implementation in an air cooled environment. The array provided is an N dimensional array of byte wide processing units each coupled with an adequate segment of byte wide memory and control logic. A partitionable section of the array containing several processing units are contained on a silicon chip arranged with "Picket"s, an element of the processing array preferably consisting of combined processing element with a local memory for processing bit parallel bytes of information in a clock cycle. A Picket Processor system (or Subsystem) comprises an array of pickets, a communication network, an I/O system, and a SIMD controller consisting of a microprocessor, a canned routine processor, and a microcontroller that runs the array.Type: GrantFiled: September 6, 1994Date of Patent: October 13, 1998Assignee: International Business Machines CorporationInventors: James Warren Dieffenderfer, Peter Michael Kogge, Paul Amba Wilkinson, Nicholas Jerome Schoonover
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Patent number: 5815723Abstract: A parallel array computer provides an array of processor memory elements interconnected for transfer of data and instructions between processor memory elements. Each of the processing elements has a processor coupled with a local memory. An array controller is provided for controlling the operation of the array of processor memory elements. Each of the processor memory elements has a plurality of local autonomous operating modes and is adapted to interpret instructions from the array controller within the processor memory element.Type: GrantFiled: September 30, 1996Date of Patent: September 29, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, Thomas Norman Barker, James Warren Dieffenderfer, Peter Michael Kogge
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Patent number: 5809292Abstract: A floating point system and method according to a format that includes a sign bit, an exponent part having a plurality of bits, and a fraction part having a plurality of multi-bit blocks, wherein floating point operation is based on block shifts of the fraction part, with each shift of one block associated with an increment or decrement of the exponent part by one count. This format illustrated is implemented as a format suitable for the accuracy greater than the IEEE 32-bit floating-point format, and is intended to be implemented in machines having byte-wide (8 bit) data streams. The preferred format consists of a sign bit, 7 exponent bits and 4 fraction bytes of eight bits for a total of 40 bits. This format and implementation allows floating-point commands to be executed in a fixed small number of cycles, thus advancing the capabilities of doing floating-point arithmetic on a SIMD machine.Type: GrantFiled: June 1, 1995Date of Patent: September 15, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge
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Patent number: 5805915Abstract: A conventional SIMD processor array architecture's functions are amplified by a SIMIMD architecture where more programmable flexibility would be useful. Decision making in general and specifically classification where decision trees are common, is a problem eased by SIMIMD. A SIMD array processor having a plurality of pickets in SIMIMD mode allows each picket to occasionally execute data-dependent instructions that are different from the instructions in other pickets to greatly improve execution efficiency in decision making areas. Every element in A SIMD array of processors receives a stream of commands from the array controller. Here several mechanisms allow an array machine with individual processing elements, called pickets, to interpret some of the SIMD commands in their own unique way, giving each picket a degree of local autonomy. A resulting capability allows the pickets to execute instructions in a mode called SIMIMD.Type: GrantFiled: June 27, 1997Date of Patent: September 8, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge
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Patent number: 5765015Abstract: In arrays of processors, especially linear arrays, it is important to be able to communicate to adjacent neighbors (en masse). That is, each element of the array can communicate with its neighbor on the left simultaneously. In addition, the array processor is provided with the ability for selected elements of the array, picket processing elements, to simultaneously communicate with other elements that are further away in one dimension than the nearest neighbor in one transfer cycle. This is accomplished by causing intermediate elements to become transparent in the communication paths, thus allowing data to "slide" through intermediate nodes to the destination node. This system can be used in the implementation of fault tolerance in the array of elements.Type: GrantFiled: June 1, 1995Date of Patent: June 9, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, Thomas Norman Barker, James Warren Dieffenderfer, Peter Michael Kogge
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Patent number: 5765011Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: April 26, 1994Date of Patent: June 9, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5765012Abstract: A controller for a SIMD processor array that can execute instructions within each processing element is described. This three stage hierarchical controller executes instructions at the function, routine, and micro-level, to maximize the effectiveness of processing within the array elements themselves. The routine sequencer is hardwired to perform looping and flow control operations using DO/WHILE, IF/THEN/ELSE, and GO-SUB constructs. A pipeline is provided to maintain a steady flow of commands to the array, and means is provided to monitor command execution progress and to provide feedback of progress to the stages of the controller.Type: GrantFiled: August 18, 1994Date of Patent: June 9, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, Thomas Norman Barker, James Warren Dieffenderfer, Peter Michael Kogge, Donald Michael Lesmeister, Robert Reist Richardson, Vincent John Smoral
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Patent number: 5761523Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: June 2, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5754871Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: May 19, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5752067Abstract: Parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, or ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: May 12, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5717943Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 5, 1995Date of Patent: February 10, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christopher Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson
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Patent number: 5717944Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: February 10, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5713037Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.Type: GrantFiled: June 7, 1995Date of Patent: January 27, 1998Assignee: International Business Machines CorporationInventors: Paul Amba Wilkinson, James Warren Dieffenderfer, Peter Michael Kogge, Nicholas Jerome Schoonover
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Patent number: 5710935Abstract: A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.Type: GrantFiled: June 6, 1995Date of Patent: January 20, 1998Assignee: International Business Machines CorporationInventors: Thomas Norman Barker, Clive Allan Collins, Michael Charles Dapp, James Warren Dieffenderfer, Donald George Grice, Peter Michael Kogge, David Christopher Kuchinski, Billy Jack Knowles, Donald Michael Lesmeister, Richard Ernest Miles, Richard Edward Nier, Eric Eugene Retter, Robert Reist Richardson, David Bruce Rolfe, Nicholas Jerome Schoonover, Vincent John Smoral, James Robert Stupp, Paul Amba Wilkinson