Abstract: A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip.

Abstract: A dual priority switching apparatus for making input port to output port connections on a requested basis quickly and dynamically, in a standard mode from any one of the input ports to a fixed number of subsets of multiple output ports simultaneously, or in a broadcast mode from any one of the input ports to all output ports simultaneously. The apparatus permits multiple broadcasts to be queued at the individual switching apparatus which resolves the broadcast contention on a synchronous priority driven basis that permits one broadcast to follow the other at the earliest possible moment and the quickest possible speed. The apparatus permits multiple multi-cast operations to occur simultaneously within the network. The multi-cast function permits subsets of nodes assigned to the same tasks to communicate among themselves without involving other nodes that are not in its own subset. Hardware circuitry detects and corrects deadlock conditions in the multi-stage network.

Abstract: A data communication bus structure where all module-to-module control information is grouped into two sets of lines, defined as sub-buses, wherein signal contents of the sub-buses change only at well-defined times, under the control of two other lines which themselves simply govern the transfer of control information relative to the communication. The bus structure is symmetrical with one type of each line driven by each of the two modules involved in the communication. Arbitrary standard error detecting/correcting encodings may be used on the bus to overcome possible bus failures with no change to the basic bus communications protocol.An independent bus monitor observes all communications over the bus, observes when an improper signaling exchange takes place, and isolates the module most responsible for the fault.