Patents by Inventor Peter N Ehlig
Peter N Ehlig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6996747Abstract: A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.Type: GrantFiled: January 7, 2003Date of Patent: February 7, 2006Assignee: Texas Instruments IncorporatedInventors: Gary L. Swoboda, Peter N. Ehlig
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Patent number: 6986028Abstract: A digital system is provided with means and methods for executing an instruction type wherein context information that pertains to that type instruction is automatically saved and restored during execution of the instruction type.Type: GrantFiled: July 17, 2002Date of Patent: January 10, 2006Assignee: Texas Instruments IncorporatedInventors: Peter N. Ehlig, Alexander Tessarolo
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Patent number: 6986142Abstract: A data processing device includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.Type: GrantFiled: September 14, 2000Date of Patent: January 10, 2006Assignee: Texas Instruments IncorporatedInventors: Peter N. Ehlig, Frederic Boutaud, James F. Hollander
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Patent number: 6918025Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: January 6, 2003Date of Patent: July 12, 2005Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6768669Abstract: A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but no ROM, to have non-volatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.Type: GrantFiled: September 17, 2002Date of Patent: July 27, 2004Assignee: Texas Instruments IncorporatedInventors: James T. Schmidt, Joe F. Sexton, Peter N. Ehlig
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Publication number: 20040052103Abstract: A conventional volatile SRAM cell is modified into a non-volatile, read only memory cell. This permits a device whose design currently includes on-chip SRAM, but no ROM, to have nonvolatile, read only memory with minimal redesign and development effort. The modifications made to the already present SRAM are fairly minimal resulting in much of the modified SRAM being largely unchanged. Because existing on chip, volatile memory is used largely as is with fairly minimal modifications to make the memory non-volatile, the time-to-market for such a device is much shorter than it would have been had the device been redesigned to include conventional ROM.Type: ApplicationFiled: September 17, 2002Publication date: March 18, 2004Applicant: Texas Instruments IncorporatedInventors: James T. Schmidt, Joe F. Sexton, Peter N. Ehlig
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Publication number: 20030226002Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.Type: ApplicationFiled: January 6, 2003Publication date: December 4, 2003Inventors: Frederic Boutaud, Peter N. Ehlig
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Publication number: 20030200423Abstract: A digital system is provided with means and methods for executing an instruction type wherein context information that pertains to that type instruction is automatically saved and restored during execution of the instruction type.Type: ApplicationFiled: July 17, 2002Publication date: October 23, 2003Inventors: Peter N. Ehlig, Alexander Tessarolo
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Publication number: 20030196144Abstract: A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.Type: ApplicationFiled: January 7, 2003Publication date: October 16, 2003Inventors: Gary L. Swoboda, Peter N. Ehlig
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Patent number: 6567910Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.Type: GrantFiled: February 12, 1999Date of Patent: May 20, 2003Assignee: Texas Instruments IncorporatedInventors: Alexander Tessarolo, Peter N. Ehlig, Glenn Harland Hopkins, Venkatesh Natarajan
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Patent number: 6546505Abstract: A data processing device including a semiconductor chip, an electronic processor on-chip and an on-chip condition sensor connected to the electronic processor for analysis of the operations.Type: GrantFiled: July 1, 1999Date of Patent: April 8, 2003Assignee: Texas Instruments IncorporatedInventors: Gary L. Swoboda, Peter N. Ehlig
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Publication number: 20020112144Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.Type: ApplicationFiled: February 12, 1999Publication date: August 15, 2002Inventors: ALEXANDER TESSAROLO, PETER N. EHLIG, GLENN HARLAND HOPKINS, VENKATESH NATARAJAN
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Patent number: 6334181Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: July 23, 1999Date of Patent: December 25, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6311264Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: October 30, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6263418Abstract: A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: July 17, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6263419Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: July 17, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6253307Abstract: A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.Type: GrantFiled: August 10, 1994Date of Patent: June 26, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6249859Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: June 19, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6249860Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: June 19, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig
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Patent number: 6247111Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.Type: GrantFiled: November 1, 1999Date of Patent: June 12, 2001Assignee: Texas Instruments IncorporatedInventors: Frederic Boutaud, Peter N. Ehlig