Abstract: One embodiment of the present invention provides an integrated memory device comprising a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and bitlines, wherein the number of memory blocks including a first set of memory blocks the memory cells thereof having a first random access time and a second set of memory blocks the memory cells thereof having a second random access time, wherein the second random access time is smaller that the first random access time.

Abstract: The present invention provides a method for fabricating a semiconductor structure having the steps of: providing a semiconductor substrate (1) made of silicon with a first hard mask layer (10; 10?) made of silicon oxide and an overlying second hard mask layer (15; 15?) made of silicon; providing a masking layer (30; 30?) made of silicon oxide above and laterally with respect to the second hard mask layer (15; 15?) made of silicon and above an uncovered edge region (RB) of the semiconductor substrate (1); providing a photoresist mask (25) above the masking layer (30; 30?) with openings corresponding from trenches (DT) to be formed in the semiconductor substrate (1); opening the masking layer (30; 30?) in a first plasma process using the photoresist mask (25), the edge region (RB) being covered by a shielding device (AR); opening the first hard mask layer (10; 10?) and second hard mask layer (15; 15?) in a second and third plasma process; and forming the trenches (DT) in the semiconductor substrate (1) in a fou

Abstract: One embodiment of the invention relates to a test structure for testing an integrated circuit with a tester unit that has one or more connecting lines to connect the integrated circuit, wherein a test signal and/or a supply voltage is applied to the integrated circuit for the purposes of testing, and an interference unit connected to at least one of the connecting lines which applies an interference signal to the connecting line to reduce the quality of the test signal and/or the quality of the supply voltage.

Abstract: In a memory circuit integrated on a semiconductor chip, an interface system is formed between the connection pads and associated internal signal lines and contains a respective separate and complete interface circuit for each of at least two different modes of operation of the memory circuit. Each interface circuit is arranged distributed over a plurality of spaced sections of the chip surface such that sections of different interface circuits alternate with one another. Only the interface circuit which is associated with the mode of operation which is desired when the memory circuit is being used is operatively connected between the connection pads and the associated internal signal lines by metallizations in the topmost metallization plane.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: An integrated memory includes memory cells arranged in a memory cell array and a read/write amplifier for evaluating and amplifying data signals of the memory cells that are being read out or written to. An error correction circuit is connected to the read/write amplifier. Data signals of selected memory cells that are to be read out or written are received by the error correction circuit, checked for errors, and in the case of a detected erroneous data signal, the erroneous data signal is corrected by being inverted and is output. The memory, even in the case of a defective memory cell, in particular a memory cell with a variable memory cell time or retention time (also called VRT-Variable Retention Time), can nevertheless largely be operated reliably.

Abstract: A configuration for the transmission of signals includes a data processing device and a functional unit, which are connected to a first and second bus system, respectively, for the respective transmission of signals with different frequencies. A transmission unit is connected to the data processing device through the first bus system and to the functional unit through the second bus system, for the transmission and conversion of signals between the data processing device and the functional unit. It additionally serves for the electrical decoupling of the first bus system and the second bus system. As a result, independently of the electrical properties of the functional unit, a high data throughput is made possible in conjunction with still good detectability of the signals to be transmitted.

Abstract: An integrated dynamic memory has word lines and bit lines as well as at least one global bit line, which is disposed in the memory cell array in the same sense as the bit lines. A voltage amplifier is connected to one of the bit lines for amplification of a data signal to a first voltage level which is not sufficient for writing the data signal back to the selected memory cell, and for outputting the amplified data signal to the global bit line. The global bit line is connected to a read amplifier for amplification of the data signal to a second voltage level that, in contrast, is sufficient for writing back the data signal. The hierarchical amplification concept allows rapid and reliable amplification of data signals that are to be read out, even if the integration density of the memory cells is high.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.

Abstract: An integrated clock generator, particularly for driving a semiconductor memory with a test signal, in which a delay locked loop is provided which, in a first mode of operation, synchronizes an input signal with a reference signal and, in a second, freewheeling mode of operation, uses a connected adder to form a precisely settable delay between the test signal and the reference signal. To change over between the first mode of operation and the second mode of operation, a selection circuit is provided. The delay locked loop is connected to the I/O interface of the integrated circuit, so that the BIST data produced are advantageously available directly at the input of the semiconductor memory. The principle described affords a simple way of providing test signals which have a highly precise delay with respect to a reference signal, as is necessary for DRAMs with a great storage density, for example.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.

Abstract: A memory configuration has at least two memories connected to one another. In the event of a memory cell access, it is ascertained in a comparison circuit of the first memory whether the address applied to a first communications interface of the memory corresponds to an address of data stored in the first memory. In the event of non-correspondence of the addresses, the address of the requested data is transferred by a control circuit via a second communications interface, which can be operated independently of the first communications interface, to the second identical memory. The requested data are received from the second memory via the second communications interface of the first memory and output via the first communications interface of the first memory. Point-to-point connections enable a high data transfer rate of the memory configuration and hence a high data throughput with good signal quality.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable offset registers, with a multiplexer circuit and a selection and combination circuit, on the basis of input signals which are fed in at low frequency and in parallel by the test unit. Simple address changes and address jumps can be realized at a high clock frequency in a very flexible manner.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: A circuit configuration for generating control signals for testing high-frequency synchronous digital circuits, especially memory chips, is described. A p-stage shift register which is clocked at a clock frequency corresponding to the high clock frequency of the digital circuit to be tested has connected to its parallel loading inputs p logical gates which logically combine a static control word with a dynamic n-position test word. The combined logical value is loaded into the shift register at a low-frequency loading clock rate so that a control signal, the value of which depends on the information loaded into the shift register in each clock cycle of the clock frequency of the latter is generated at the serial output of the shift register.

Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.