Abstract: A configuration for producing test signals for testing semiconductor chips includes a clock signal source for producing a clock signal, and a tester. The test signals are produced on the respective semiconductor chips in a precise temporal sequence with respect to the clock signal. The temporal sequence of the test signals on a respective one of the semiconductor chips is determined from the clock signal. Latches are connected downstream of each of the signal inputs for each of the test signals. A DLL unit uses the clock signal to produce a delayed clock signal to activate the latches. Switches to be driven by a test mode signal are disposed in parallel with the latches. A method for producing test signals for testing semiconductor chips includes the steps of supplying test signals to semiconductor chips in a precise temporal sequence with respect to a clock signal, and determining from the clock signal the temporal sequence of the test signals on each of the semiconductor chips.

Abstract: An integrated memory includes memory cells arranged in a memory cell array and a read/write amplifier for evaluating and amplifying data signals of the memory cells that are being read out or written to. An error correction circuit is connected to the read/write amplifier. Data signals of selected memory cells that are to be read out or written are received by the error correction circuit, checked for errors, and in the case of a detected erroneous data signal, the erroneous data signal is corrected by being inverted and is output. The memory, even in the case of a defective memory cell, in particular a memory cell with a variable memory cell time or retention time (also called VRT-Variable Retention Time), can nevertheless largely be operated reliably.

Abstract: A semiconductor memory of an integrated circuit has memory cells that are combined to form individually addressable normal units and redundant units for replacing normal units. The semiconductor memory has a selection circuit for selecting one of the redundant units. A non-volatile first memory unit for storing an address, which can be programmed by an energy beam, of a normal unit to be replaced is provided. A non-volatile second memory unit for storing an address, which can be programmed via electrical contact is also provided. The first and second memory units are connected to the selection circuit for transmitting their respective stored information to the selection circuit. A repair can thus be carried out on the unhoused semiconductor memory and on the housed semiconductor memory. Since only a sufficient portion of all the redundant circuits to be provided are configured in such a way, this allows a space requirement that is smaller overall.

Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

Abstract: A configuration for the transmission of signals includes a data processing device and a functional unit, which are connected to a first and second bus system, respectively, for the respective transmission of signals with different frequencies. A transmission unit is connected to the data processing device through the first bus system and to the functional unit through the second bus system, for the transmission and conversion of signals between the data processing device and the functional unit. It additionally serves for the electrical decoupling of the first bus system and the second bus system. As a result, independently of the electrical properties of the functional unit, a high data throughput is made possible in conjunction with still good detectability of the signals to be transmitted.

Abstract: A memory configuration has at least two memories connected to one another. In the event of a memory cell access, it is ascertained in a comparison circuit of the first memory whether the address applied to a first communications interface of the memory corresponds to an address of data stored in the first memory. In the event of non-correspondence of the addresses, the address of the requested data is transferred by a control circuit via a second communications interface, which can be operated independently of the first communications interface, to the second identical memory. The requested data are received from the second memory via the second communications interface of the first memory and output via the first communications interface of the first memory. Point-to-point connections enable a high data transfer rate of the memory configuration and hence a high data throughput with good signal quality.

Abstract: A configuration for carrying out burn-in processing for semiconductor devices at the wafer level. To this end, BIST units are allocated to the individual semiconductor chips, so that the burn-in processing operations can take place by use of a self-test and complicated probe cards can be dispensed with.

Abstract: An integrated dynamic memory has word lines and bit lines as well as at least one global bit line, which is disposed in the memory cell array in the same sense as the bit lines. A voltage amplifier is connected to one of the bit lines for amplification of a data signal to a first voltage level which is not sufficient for writing the data signal back to the selected memory cell, and for outputting the amplified data signal to the global bit line. The global bit line is connected to a read amplifier for amplification of the data signal to a second voltage level that, in contrast, is sufficient for writing back the data signal. The hierarchical amplification concept allows rapid and reliable amplification of data signals that are to be read out, even if the integration density of the memory cells is high.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: A method and a configuration are provided for compensating for parasitic current losses in an MRAM memory cell array. Individual word lines and bit lines are supplied with currents which are proportioned in such a way that a total current level at respective points of intersection between the word lines and the bit lines is substantially constant.

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which a plurality of memory cell blocks are supplied with operating voltages that differ from one another in each case. This results in that the chip voltage supply of about 2 to 3 V can be better utilized. The memory cell blocks are formed of memory cells disposed at cross-over points of word lines and bit lines.

Abstract: A method and a device for reading and for checking the time position of a data response read out from a memory module to be tested, in particular a DRAM memory operating in DDR operation. In a test receiver, the data response from the memory module to be tested is latched into a data latch with a data strobe response signal that has been delayed. A symmetrical clock signal is generated as a calibration signal. The calibration signal is used to calibrate the time position of the delayed data strobe response signal with respect to the data response. The delayed data strobe response signal is used for latching the data response. The delay time is programmed into a delay device during the calibration operation and also supplies a measure for testing precise time relationships between the data strobe response signal (DQS) and the data response.

Abstract: A configuration for testing chips includes a printed circuit board having conductive probe needles to electrically connect the printed circuit board to chips and for testing the chips on the printed circuit board in parallel, some of the probe needles configured as dummy needles for mechanically self-aligning the chips. The board is configured closely to the application such that many chips (1) can be tested simultaneously in parallel. The chips can have markings or depressions to be engaged with free ends of the dummy needles remote from the board. Adapters can be disposed between the probe needles and the chips. Also, the chips can have structures disposed thereon between the probe needles and the chips. The board can have alignment aids for orienting the chips.

Abstract: A substrate includes a memory and a testing device for testing the memory. The testing device includes an interpreter element that operates and tests the memory in accordance with a test program. The test program command codes are stored in the untested memory cell array of the memory that will be tested. The advantage of the testing device consists, inter alia, in the fact that the testing device no longer needs to be adapted to changed hardware properties of the chip generation or fabrication lines because the test program, which is suitable for the respective chip type, is stored as a variable code on the respective memory which is to be tested. It is thus also possible to test various memory chip types with the same testing device.

Abstract: An integrated clock generator, particularly for driving a semiconductor memory with a test signal, in which a delay locked loop is provided which, in a first mode of operation, synchronizes an input signal with a reference signal and, in a second, freewheeling mode of operation, uses a connected adder to form a precisely settable delay between the test signal and the reference signal. To change over between the first mode of operation and the second mode of operation, a selection circuit is provided. The delay locked loop is connected to the I/O interface of the integrated circuit, so that the BIST data produced are advantageously available directly at the input of the semiconductor memory. The principle described affords a simple way of providing test signals which have a highly precise delay with respect to a reference signal, as is necessary for DRAMs with a great storage density, for example.

Abstract: In the method for testing a memory cell, a test voltage is applied to a memory cell and the test voltage is changed, preferably in incremental or decremental steps, during the testing. From the shape of the hysteresis of the memory cell it is determined whether or not the memory cell is a weak or substandard memory cell.

Abstract: The present invention relates to an integrated circuit which is connected to a reference-ground potential and to a supply potential. Since differing activity in the integrated circuit results in a fluctuating current being drawn by the integrated circuit, current surges may arise on the supply potential. To prevent current surges on the supply potential, a controllable load is produced together with the integrated circuit, with the result that the power drawn by the combination of integrated circuit and the load is approximately constant.

Abstract: An integrated memory has reference word lines, word lines and redundant word lines. It has a programmable activation unit whose programming state governs whether the redundant word line having redundant memory cells connected thereto replaces one of the word lines having memory cells connected thereto or the reference word line having reference cells connected thereto during operation of the memory.

Abstract: A test configuration for testing a plurality of integrated circuits, in particular fast semiconductor memory modules located on a wafer, in parallel. The test configuration includes a carrier board for bringing up electrical signal lines belonging to a test system, contact-making needles for producing electrical connections with contact areas on the circuits to be tested, and a plurality of active modules that are arranged on the carrier board. The active modules are each assigned to one of the circuits to be tested in parallel, and are each case inserted into the signal path between the test system and the associated circuit to be tested. In a preferred embodiment, the active modules are arranged at least partly overlapping, based on a direction at right angles to the plane of the carrier board.

Abstract: A system and a method for testing fast synchronous digital circuit with an additional built outside self test semiconductor chip disposed between a test device and circuit under test. The chip has a switching/detection unit that tests the chip based on external criteria between a first normal operating mode in which the chip tests the circuit to be tested, and a second operating mode in which programmable registers of the register unit of a receiver of the chip are programmed by the external test device. The registers store constants and variables for generating the test signals and for evaluating them. The chip generates test signals and transceiver for sending the test signals and receiving response signals generated thereby.