Abstract: A tester board system that includes a frame upon which a plurality of motherboards can be inserted for the purposes of BI and other types of component testing. Each motherboard has memory channels that can accommodate a plurality of memory components for testing, and the memory channels are connected to a CPU. In preferred embodiments, the CPU is on the underside of the motherboard and the memory channels on the top side of the motherboard.

Abstract: A chip or wafer has at least two electrically conducting alignment marks that contact at least two electrically conductive probe needles on a probe card. The at least two electrically conducting alignment marks each have an electrical signal that can transfer from the alignment marks to the electrically conductive probe needles. The two electrical signals can have a different voltage level or a different signal frequency than one another. The electrical signals are used to calculate a rotational deviation and/or lateral deviation of the chip or wafer relative to the probe card for precise wafer alignment.

Abstract: A motherboard assembly for testing wafers is described. The motherboard assembly includes a probe card having a plurality of needles disposed in a center region and a plurality of micro connectors disposed outside the center region. Each micro connector is communicatively coupled with a plurality of needles. The motherboard assembly also includes a lower motherboard comprising a plurality of tiles, each tile having at least one processor and at least one memory channel. Each memory channel is communicatively coupled with a micro connector of the probe card. A gap vertically separates and insulates the lower motherboard from the probe card. A wafer is sized and dimensioned to rest on the needles of the probe card for testing.

Abstract: A motherboard assembly for testing memory components is described. The motherboard assembly has at least one CPU communicatively coupled with at least one memory channel, and a memory controller or BIOS programmed to continue booting in the presence of memory component failures. The memory controller or BIOS skips read/write training procedures when a failure is detected, and uses preset values for PHY registers from a previous successful booting procedure to continue the current booting without powering off. The memory controller or BIOS is also programmed to provide adjustable retention settings and adjustable speed settings without rebooting or powering off.

Abstract: A tester board system that includes a frame upon which a plurality of motherboard assemblies can be inserted for the purposes of BI and other types of component testing. Each motherboard assembly has memory channels disposed on an upper motherboard that can accommodate a plurality of memory components for testing, and the memory channels are connected to a CPU. The CPU is disposed on a lower motherboard and the memory channels are connected to the CPU via communication connectors that are passed via a connection column between the upper and lower motherboards.

Abstract: A tester board system that includes a frame upon which a plurality of motherboard assemblies can be inserted for the purposes of BI and other types of component testing. Each motherboard assembly has memory channels disposed on an upper motherboard that can accommodate a plurality of memory components for testing, and the memory channels are connected to a CPU. The CPU is disposed on a lower motherboard and the memory channels are connected to the CPU via communication connectors that are passed via a connection column between the upper and lower motherboards.

Abstract: A tester board system that includes a frame upon which a plurality of motherboards can be inserted for the purposes of BI and other types of component testing. Each motherboard has memory channels that can accommodate a plurality of memory components for testing, and the memory channels are connected to a CPU. In preferred embodiments, the CPU is on the underside of the motherboard and the memory channels on the top side of the motherboard.

Abstract: The invention relates to an integrated memory circuit having a memory cell array comprising memory cells arranged on word lines and bit lines, and having a repair circuit for repairing a single bit error in one of the memory cells, the repair circuit comprising: an error memory for storing an item of repair information, an assignment unit in order, when accessing an address of the memory cell array, depending on the repair information, to access either a memory area of the memory cell array or a redundancy memory area, and a test unit for determining the repair information.

Abstract: In a method for repairing a memory component, data retention times of regular memory cells are determined. Weak regular memory cells having a data retention time that is shorter than a predetermined limit value are determined. A device is programmed in such a manner that a write or read access to the weak regular memory cell is simultaneously also effected for a redundant memory cell in order to jointly read from, or write to, the weak regular memory cell and the redundant memory cell.

Abstract: The invention relates to a memory circuit comprising regular memory areas and redundant memory areas, redundancy circuits in each case being assigned to the redundant memory areas, each redundancy circuit having permanently settable storage elements in order, in a first setting state, to address the assigned redundant memory area in the event of addressing of the regular memory area with a memory address determined by the first setting state, each redundancy circuit, in a second setting state, addressing the assigned redundant memory area in a manner dependent on an activation signal.

Abstract: Apparatuses and methods for transmitting and receiving a data signal on a line pair having a first transmission line and a second transmission line are provided. In one embodiment, a data signal which represents the data to be transmitted by means of a sequence of first and second signal levels is applied to the first transmission line, and a reference signal which changes between a first and a second reference level only when a level change between the first and the second signal level is suppressed between two successive signal levels of the data signal on the first transmission line is applied to the second transmission line.

Abstract: A memory component comprises a plurality of memory cells that are each assigned an address, and an address memory for storing numerical values which are uniquely related to addresses of defective memory cells. An address converter having an input for receiving a first address and an output for outputting a second address is designed in such a way that the second address output at its output is dependent on the first address received at its input and on the numerical values stored in the address memory, each first address being uniquely assigned a second address. An address bus, which is connected to the output of the address converter, transfers the second address to an input of an address decoder, which is designed for selecting a memory cell to which the second address is assigned.

Abstract: Multichip devices and methods of making the same. In one embodiment, a chip stack is sandwiched between first and second redistribution substrates. The chip stack is electrically connected to contact structures of the first redistribution substrate and the second redistribution substrate.

Abstract: The invention relates to a method for testing electrical modules. A test pattern of input signals is applied to each module to be tested as test specimen, and the actual responses of the test specimen to the test pattern is compared with the desired responses. The comparison result is evaluated for the purpose of displaying test assessments. According to one embodiment of the invention, to supply the desired responses, a reference module produced with the same design and technology as the test specimen and tested as entirely satisfactory is utilized. The same test pattern as for the test specimen is applied to the reference module. The invention furthermore relates to circuit arrangements for carrying out this method, in particular for testing data memories.

Abstract: The invention relates to a memory module having a printed circuit board; having one or more memory chips which are arranged in a first region of the printed circuit board and are contact-connected by the printed circuit board; having a buffer chip for driving the memory chips and for communicating with a system that is external to the memory module, the buffer chip being arranged in a second region of the printed circuit board and being contact-connected by the printed circuit board; wherein the first and second regions of the printed circuit board are essentially thermally decoupled from one another.

Abstract: A circuit comprises an output terminal, an output driver for providing an output signal at the output terminal, a switching device for producing one or more connections of the output terminal to a respective fixed or variable potential, and a control device for controlling the switching device, the control device being designed to produce the connection or the connections in the event of a transition in the output signal from a first logic level to a second logic level and to disconnect it at the latest when the output signal attains the second level.

Abstract: An integrated circuit has at least two supply systems, each of which is connected to an individually assigned section of the integrated circuit to supply power to the relevant section. A low-pass coupler is connected between the at least two supply systems.

Abstract: A semiconductor device includes a plurality of semiconductor chips packaged in a common housing. The semiconductor chips include signal pads to pass critical signals to respective chips and are terminated by a terminating resistance. At least one set of signal pads, arranged on different chips and in close proximity to one another, are connected and pass the same signal. The signal pads are terminated by the terminating resistance.

Abstract: A semiconductor device with a test circuit disconnected from a power supply connection to reduce leakage current, and a method of manufacture thereof. The test circuit may be used to test functional circuits on the semiconductor device, and after the tests are completed, the test circuit is disconnected from the power supply connection. The test circuit is powered by contacting a test pad with a probe that supplies power to the test circuit, in one embodiment. In another embodiment, the test circuit is disconnected from the power supply using a laser to blow a fuse in the path of the power supply connection for the test circuit. Optional features include a bleeder device coupled to the power supply input of the test circuit, and logic circuitry for setting the outputs of the test circuit to a predetermined state coupled to the outputs of the test circuit.

Abstract: A system and method are provided for reducing a rate for refreshing a portion of a dynamic random access memory (DRAM). The method includes storing a information for distinguishing between a first portion of a DRAM requiring refresh at a first rate and a second portion of said DRAM permitting refresh at a second rate lower than the first rate. The stored information is then accessed to refresh the first portion of the DRAM at the first rate and to refresh the second portion at the second rate. The information can be generated from post-fabrication stress testing such that most of the DRAM can be refreshed at the lower rate and only the portion requiring more frequent refresh is refreshed at the higher rate.