Abstract: An array of multiple off chip drivers on an integrated circuit (IC) chip has reduced synchronous switching output timing error (TSSO) at high speeds of operation. The array includes a pair of low resistance buses to provide charge and discharge paths for the outputs, a plurality of terminals connecting the respective drivers between the buses, the resistance of each terminal being substantially greater than the resistance of either bus, and a plurality of capacitors connected internally of the respective drivers. Each driver has an input for receiving binary data from a memory unit and an output terminal which is switched in accordance with the binary input data to a higher or lower voltage level. There are a plurality of transistor switches within each driver which selectively couple a capacitor to the output terminal when it is driven high and at the same time couple another capacitor to one of the buses, and vice versa when the output terminal is driven low.

Abstract: A memory bank, in accordance with the present invention includes a plurality of memory sub-units, each memory sub-unit being divided by sense amplifier banks wherein adjacent memory sub-units share the sense amplifier bank therebetween. Redundancy regions are also included which are disposed in the memory sub-units and sharing circuitry therewith. The redundancy regions are located at a first end portion and a second end portion of the memory bank, the first and second end portions being disposed at opposing ends of the memory bank. A central sense amplifier bank is disposed between a first half and a second half of the memory bank wherein failed devices in the first half of the memory bank are replaced by a device in the redundancy region at the first end portion and failed devices in the second half of the memory bank are replaced by a device in the redundancy region at the second end portion such that sense amplifier contention is prevented for the central sense amplifier bank.

Abstract: An OCD circuit with stacked transistor that is gated to switch on prior to the switching on of the transistors which the stacked transistor protects. The gating of the stacked transistor results in the reduction of the total OCD output capacitance.

Abstract: Disclosed is a semiconductor memory having a main memory cell array and redundant memory cells, with a plurality of fuses that can be physically separated from their associated fuse latches. Physical separation is possible by incorporating serial transfer circuitry to serially transfer fuse data from the fuses towards the latches. As a result, only a small number of wires are needed to connect the fuses to the fuse latches, allowing for flexible fuse placement within the memory.