Abstract: Methods and circuits for biasing a transconducting cell to operate in a subthreshold state so as to have a desired high transconductance, and systems including a master cell for generating a regulated bias voltage and one or more transconducting slave cells biased in subthreshold by the bias voltage. An example of such system is an inverting voltage amplifier (offering low power consumption, low noise, good stability, and high gain). The bias voltage is generated to be independent of process and environmental variations by servoing an unregulated supply voltage, and preferably has lower magnitude relative to ground than the supply voltage. Preferably, the master cell includes transistors in which a constant current density is maintained, and this current density is replicated in each slave cell biased by the master cell.

Abstract: A comparator including one or more transconducting inverters, each inverter biased to operate in a subthreshold state so as to have a desired high transconductance. In preferred embodiments, the transconducting inverter is biased in subthreshold by a bias voltage whose value is independent of process and environmental variations (so that the subthreshold current density in the inverter remains fixed despite supply voltage variations and other process and environmental variations). The bias voltage is generated by servoing an unregulated supply voltage so that the bias voltage has lower magnitude (relative to ground potential) than the supply voltage. The reduced-magnitude, regulated bias voltage precisely regulates at least one transistor in each inverter by forcing a constant current density therein, thereby causing the cell to operate in subthreshold.

Abstract: An adaptive battery charger circuit including a state machine adjusts the charging current in accordance with the battery charge acceptance. The battery charging cycle includes an initial charging phase characterized by a relatively high charge acceptance, an intermediate charging phase characterized by a decreasing charge acceptance and a rising battery temperature, and a final charging phase characterized by the battery being at substantially full charge and the charge acceptance approaching zero. Each charging phase corresponds to one or more states of the state machine. Multiple sets of conditions causing transitions between the states of operation are derived from a model of a battery under charge which relates charge acceptance, battery temperature, and cumulative supplied charge. During the intermediate charging phase, the charging current is adjusted to maintain a predetermined battery temperature for a predetermined duration.

Abstract: An analog-to-digital converter (ADC) generates multiple analog waveforms, preferably as voltage ramps, that progressively increase in signal value over time but at different rates of increase. The ramp with the greatest slope is initially compared with an input signal sample until the ramp exceeds the sample, at which time the system switches to the ramp with the next greatest slope for comparison with the input. The operation then repeats, with the system switching to the next lower ramp each time the current ramp exceeds the input. Both the number of ramp switching events that occur during a sample cycle, and the clock count at the time of the most recent ramp switch, are recorded and used respectively as the most and least significant bits of a digital output. The switching event count proceeds from an initial maximum value from which it subtracts at each switching event, while the clock count builds up from an initial minimum value.

Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascaded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.

Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascoded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.

Abstract: A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascoded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.

Abstract: A 16-bit D/A converter formed on a single monolithic IC chip and having two cascaded stages each including a 256-R resistor-string DAC. The first stage employs a switch selector system capable of selecting any two adjacent taps of the resistor string to produce a segment voltage to be applied across the second stage resistor string. The resistor strings are formed as elongate thin film strips configured as a single, unbent body having integral voltage tap nipples evenly-spaced along both sides of the strip. Buffer amplifiers between the cascaded stages incorporate NMOS and PMOS-cascoded bipolar current sources in a non-epitaxial structure on a P-type substrate.

Abstract: A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

Abstract: A two-stage analog-to-digital converter wherein the first stage is a resistor-string d-to-a converter controlled by a successive-approximation register, functioning in a first phase of the conversion operation to determine a set of higher order bits of the digital output signal. The second stage is a dual-slope integrating-type a-to-d converter functioning in a second phase of the conversion operation to determine the remaining lower-order bits of the digital output signal. The dual-slope converter receives a reference signal derived from two adjacent junction points of the first-stage resistor-string d-to-a converter corresponding to the higher order bits determined in the first phase of operation, thereby to assure high resolution performance.

Abstract: A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

Abstract: A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e.g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I.sup.2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

Abstract: A temperature-compensated IC voltage reference comprising a Zener diode serving as the principal voltage source, in combination with a compensating voltage source including a transistor providing a forward-biased junction, and control circuitry. The compensating voltage is summed with the Zener voltage to produce a reference voltage. The compensating voltage source includes an adjustment element for trimming the reference output to a specified voltage, and the control circuitry operates with that adjustment element to automatically produce optimum temperature compensation when the output has been adjusted to the specified value.