Abstract: Circuits, methods, and media for providing calibrated delta-sigma modulators are provided. In some embodiments, circuits for a delta-sigma modulator are provided, the circuits comprising: an analog-to-digital converter that produces an output having multiple bits; a digital-to-analog converter having an input having multiple bits; a switch coupled between the output the input that can be used to configure connections between the bits of the output and the bits of the input; a hardware processor that: for multiple iterations, sets a configuration of the switch, samples the bits of the output to produce sample values for each bit of the bits of the output, and calculates an average of the sample values for each of the bits of the output values; computes weights for each of the bits of the output values; and calculates weighted output values for every value of the outputs.

Abstract: Circuits and methods for switched mode operational amplifiers are provided. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; a first pulse width modulator (PWM) having an input coupled to the output of the amplifier and using a first periodic reference signal waveform; and a second PWM having an input coupled to the output of the amplifier and using a second periodic reference signal waveform, wherein the second periodic reference signal waveform is 180 degrees out of phase from the first periodic reference signal waveform. In some embodiments, circuits are provided, the circuits comprising: an amplifier having an output; and a plurality of pulse width modulators (PWMs) each having an input coupled to the output of the amplifier and using a corresponding unique one of a plurality of periodic reference signal waveforms, wherein the plurality of periodic reference signal waveforms are shifted in phase.

Abstract: Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together.

Abstract: Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an RZ signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode, that receives the RZ signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.

Abstract: Circuits and methods for performing harmonic rejection mixing are provided. In some embodiments, the circuit comprises: a first amplifier that amplifies a received signal at a first gain; a second amplifier that amplifies the received signal at a fraction of the first gain; a mixer that receives a local oscillator signal having a first fundamental frequency and the first amplifier output, and outputs a first mixed signal; a second mixer that receives a second local oscillator signal having a fundamental frequency that is a multiple of the first fundamental frequency and the second amplifier output, and outputs a second mixed signal; and an output stage that receives the first and second mixed signals and outputs a sum of the first and second mixed signals.

Abstract: Circuits and methods comprising: a radio frequency amplifier that powers off in response to an enable signal; a demodulator that outputs an RZ signal; an all-digital clock and data recovery circuit comprising: a phase detector that includes a tri-state phase frequency detector for use when in an acquisition mode and a Hogge phase detector for use when in a communication mode, that receives the RZ signal, and that outputs a phase detector output from the tri-state phase frequency detector when in the acquisition mode and from the Hogge phase detector when in the communication mode, a loop filter that receives the phase detector output from the phase detector and produces a loop filter output that is the sum of a proportional path of the loop filter and an integral path of the loop filter, and a numerical controlled oscillator that receives the loop filter output and produces the enable signal.

Abstract: An integrated communications system. A substrate having a receiver disposed on the substrate for converting a received signal to an IF signal, a digital IF demodulator disposed on the substrate and coupled to the receiver for converting the IF signal to a demodulated baseband signal, and a transmitter disposed on the substrate operating in cooperation with the receiver to establish a two way communications path.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-bold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits embodiments such as operational transconductance amplifiers (1101, 1102, 1103), biasing circuits, integrators (1113, 1123, 1133), continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Circuits (FIG. 1) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (FIG. 1) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (M1A, M1B) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.

Abstract: Circuits that operate with power supplies of less than 1 volt are presented. More particularly, circuits that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (310, 312, etc.) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers (346), biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Methods and systems are provided for reducing circuit area. Some embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path crosses itself at least two points and wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane. Other embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane, and wherein the circuit comprises a signal path that is rake-shaped and crosses the path of the inductor at substantially perpendicular angles.

Abstract: Some embodiments provide a multilayer integrated circuit, including: a semiconductor substrate including a plurality of channels extending into the substrate from a surface of the substrate; a distributed capacitor including a plurality of gates formed on the surface of the substrate over the channels, and further including an insulator between the gates and the channels, the gates being spaced apart along the surface of the substrate; an interconnect layer formed over the distributed capacitor, the interconnect layer including a plurality of conductors, at least a first conductor being connected to at least some of the gates and at least a second conductor being connected to at least some of the channels; and an inductor formed over the interconnect layer, the inductor including at least conductor arranged on a layer.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits embodiments such as operational transconductance amplifiers (1101, 1102, 1103), biasing circuits, integrators (1113, 1123, 1133), continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Circuits that operate with power supplies of less than 1 Volt are presented. More particularly, circuits that operate with supply voltages near or lower than the threshold voltage of the transistors in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Circuits (FIG. 1) that operate with power supplies (VDD) of less than 1 Volt are present. More particularly, circuits (FIG. 1) that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (M1A, M1B) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers, biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor (MOS) to bipolar junction transistors may implement the techniques presented herein.

Abstract: Circuits that operate with power supplies of less than 1 volt are presented. More particularly, circuits that operate with supply voltages (VDD) near or lower than the threshold voltage of the transistors (310, 312, etc.) in those circuits are presented. Various circuits and embodiments such as operational transconductance amplifiers (346), biasing circuits, integrators, continuous-time sigma delta modulators, track-and-hold circuits, and others are presented. The techniques and circuits can be used in a wide range of applications and various transistors from metal-oxide-semiconductor to bipolar junction transistors may implement the techniques presented herein.

Abstract: Methods and systems are provided for reducing circuit area. Some embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path crosses itself at least two points and wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane. Other embodiments provide electronic devices including an inductor formed from a path having two ends that loops substantially in a plane around a center area, wherein the path defines an outer boundary of the inductor; and a circuit that is located within the outer boundary of the inductor and substantially within or adjacent to the plane, and wherein the circuit comprises a signal path that is rake-shaped and crosses the path of the inductor at substantially perpendicular angles.