Abstract: An apparatus and method are described, the apparatus comprising processing circuitry to perform data processing operations, microarchitecture circuitry used by the processing circuitry during performance of the data processing operations, and an interface to receive interrupt requests. The processing circuitry is responsive to a received interrupt request to perform an interrupt service routine, and the apparatus comprises prediction circuitry to determine a predicted time of reception of a next interrupt of at least one given type. The apparatus also comprises microarchitecture control circuitry arranged to vary a configuration of the microarchitecture circuitry between a performance based configuration and a responsiveness based configuration in dependence on the predicted time, so as to seek to increase the responsiveness of the apparatus to interrupts as the predicted time is approached.

Abstract: Coherency control circuitry (10) supports processing of a safe-speculative-read transaction received from a requesting master device (4). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache (11) of the requesting master device (4) while prohibiting any change in coherency state associated with the target data in other caches (12) in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry (10) and the second cache (12) is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.

Abstract: Presenting ancestral origin information, comprising: receiving a request to display ancestry data of an individual; obtaining ancestry composition information of the individual, the ancestry composition information including information pertaining to a proportion of the individual's genotype data that is deemed to correspond to a specific ancestry; and presenting the ancestry composition information to be displayed.

Abstract: A data processing apparatus is provided which controls the use of data in respect of a further operation. The data processing apparatus identifies whether data is trusted or untrusted by identifying whether or not the data was determined by a speculatively executed resolve-pending operation. A permission control unit is also provided to control how the data can be used in respect of a further operation according to a security policy while the speculatively executed operation is still resolve-pending.

Abstract: Examples are disclosed that relate to deferring a message based upon a target situation for message presentation. One example provides a computing device including an output subsystem including one or more output devices, an input subsystem including one or more user input devices, and a logic device. The computing device further includes memory storing instructions executable by the logic device to receive a message from a remote computing system, output a notification of the message via the output subsystem, and receive via the input subsystem a request for a deferral of the message, the request for the deferral including an annotation to be stored for a later presentation with the message.

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

Abstract: Methods and apparatus for driving flow in a microfluidic arrangement are provided. In one disclosed arrangement, the microfluidic arrangement comprises a first liquid held predominantly by surface tension in a shape defining a microfluidic pattern on a surface of a substrate. The microfluidic pattern comprises at least an elongate conduit and a first reservoir. The area of contact between the substrate and a portion of the first liquid that forms the elongate conduit defines a conduit footprint. The area of contact between the substrate and a portion of the first liquid that forms the first reservoir defines a first reservoir footprint. The size and shape of each of the conduit footprint and the first reservoir footprint are such that a maximum Laplace pressure supportable by the first liquid in the elongate conduit without any change in the conduit footprint is higher than a maximum Laplace pressure supportable by the first liquid in the first reservoir without any change in the first reservoir footprint.

Abstract: An apparatus and method are provided for processing instructions. The apparatus has execution circuitry for executing instructions, where each instruction requires an associated operation to be performed using one or more source operand values in order to produce a result value. Issue circuitry is used to maintain a record of pending instructions awaiting execution by the execution circuitry, and prediction circuitry is used to produce a predicted source operand value for a chosen pending instruction. Optimisation circuitry is then arranged to detect an optimisation condition for the chosen pending instruction when the predicted source operand value is such that, having regard to the associated operation for the chosen pending instruction, the result value is known without performing the associated operation.

Abstract: An apparatus and method are described, the apparatus comprising processing circuitry to perform data processing operations, microarchitecture circuitry used by the processing circuitry during performance of the data processing operations, and an interface to receive interrupt requests. The processing circuitry is responsive to a received interrupt request to perform an interrupt service routine, and the apparatus comprises prediction circuitry to determine a predicted time of reception of a next interrupt of at least one given type. The apparatus also comprises microarchitecture control circuitry arranged to vary a configuration of the microarchitecture circuitry between a performance based configuration and a responsiveness based configuration in dependence on the predicted time, so as to seek to increase the responsiveness of the apparatus to interrupts as the predicted time is approached.

Abstract: A data processing apparatus comprises branch prediction circuitry adapted to store at least one branch prediction state entry in relation to a stream of instructions, input circuitry to receive at least one input to generate a new branch prediction state entry, wherein the at least one input comprises a plurality of bits; and coding circuitry adapted to perform an encoding operation to encode at least some of the plurality of bits based on a value associated with a current execution environment in which the stream of instructions is being executed. This guards against potential attacks which exploit the ability for branch prediction entries trained by one execution environment to be used by another execution environment as a basis for branch predictions.

Abstract: A radio frequency (RF) circuit is provided. The RF circuit may include a variety of RF filters organized into a number of filter banks and configured to support carrier aggregation (CA) in a variety of band combinations. In examples discussed herein, the RF circuit is configured to utilize separate receive and transmit filters for filtering an RF receive signal and an RF transmit signal in a time-division duplex (TDD) band, respectively. By employing separate receive and transmit filters for the TDD band, as opposed to using an integrated receive-transmit filter, it may be possible to implement the receive and transmit filters in the RF circuit with improved impedance matching, interference rejection, and insertion loss without increasing a footprint of the RF circuit.

Abstract: A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Abstract: An apparatus 2 has a processing pipeline 4 supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure 22, 30, 36, 50, 40, 64, 44 is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry 70 triggers a subset 102 of the entries of the storage structure to be placed in a power saving state.

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

Abstract: A backlight unit for a display device comprising a chassis, a reflector affixed to the chassis, optical sheets affixed to the chassis, one or more light emitters affixed to the chassis, and optically-calibrated internal support structures. There is an air gap between the reflector and the optical sheets. The optically-calibrated internal support structures are disposed within the air gap and affixed to the chassis. The optically-calibrated internal support structures are configured to increase rigidity of the chassis, and to substantially not alter the uniformity of light emitted by the one or more light emitters through the optical sheets.

Abstract: The present invention relates to a field of genetically modified fungal cells and converting galacturonic acid to meso-galactaric acid, more precisely to a method of producing meso-galactaric acid. The invention further relates to recombinant fungal cells having a specific combination of modifications including but not limited to expression of uronate dehydrogenase enzyme, reduced D-galacturonic acid reductase activity, and furthermore reduced meso-galactaric acid catabolism, as well as uses and methods related thereto.

Abstract: The invention relates to processes for preparing isoindolin-1-one derivatives, and in particular processes for preparing (2S,3S)-3-(4-chlorophenyl)-3-[(1R)-1-(4-chlorophenyl)-7-fluoro-5-[(1S)-1-hydroxy-1-(oxan-4-yl)propyl]-1-methoxy-3-oxo-2,3-dihydro-1H-isoindol-2-yl]-2-methylpropanoic acid. The invention also relates to crystalline forms of the compound (2S,3S)-3-(4-chlorophenyl)-3-[(1R)-1-(4-chlorophenyl)-7-fluoro-5-[(1S)-1-hydroxy-1-(oxan-4-yl)propyl]-1-methoxy-3-oxo-2,3-dihydro-1H-isoindol-2-yl]-2-methylpropanoic acid and its salts.

Abstract: Methods and apparatus for controlling flow in a microfluidic arrangement are disclosed. In one arrangement, a microfluidic arrangement comprises a first liquid held predominantly by surface tension in a shape defining a microfluidic pattern on a surface of a substrate. The microfluidic pattern comprises at least an elongate conduit and a first reservoir. A second liquid is in direct contact with the first liquid and covers the microfluidic pattern. A flow of liquid is driven through the elongate conduit into the first reservoir.

Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.