Patents by Inventor Peter S. Locke

Peter S. Locke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7678258
    Abstract: An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Keith T. Kwietniak, Peter S. Locke, Darryl D. Restaino, Soon-Cheon Seo, Philippe M. Vereecken, Erick G. Walton
  • Patent number: 7227265
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 ?m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: June 5, 2007
    Assignee: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Patent number: 6979393
    Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ? or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: December 27, 2005
    Assignee: International Business Machines Corporation
    Inventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Jr., Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke
  • Publication number: 20040178077
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Publication number: 20040178078
    Abstract: Interconnect structures with copper conductors being at least substantially free of internal seams or voids are obtained employing an electroplating copper bath containing dissolved cupric salt wherein the concentration of the salt is at least about 0.4 molar and up to about 0.5 molar concentration of an acid. Also provided are copper damascene structures having an aspect ratio of greater than about 3 and a width of less than about 0.275 &mgr;m and via openings filled with electroplated copper than is substantially free of internal seams or voids.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, Steven H. Boettcher, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Christopher C. Parks, Soon-Cheon Seo, Andrew H. Simon, Erick G. Walton
  • Patent number: 6660330
    Abstract: The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: December 9, 2003
    Assignee: International Business Machines Corporation
    Inventors: Peter S. Locke, Sandra Guy Malhotra, Fenton Read McFeely, Andrew Herbert Simon, John Jacob Yurkas
  • Patent number: 6600230
    Abstract: A process for plating metal in submicron structures. A seedlayer is deposited on surfaces of submicron structures. The seedlayer is annealed at a temperature of about 80° C. to about 130° C. Metal is plated on the seedlayer.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: July 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: Cyprian E. Uzoh, Peter S. Locke
  • Patent number: 6592747
    Abstract: Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: July 15, 2003
    Assignee: International Business Machines Corporation
    Inventors: Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke
  • Publication number: 20030000850
    Abstract: Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.
    Type: Application
    Filed: June 18, 2001
    Publication date: January 2, 2003
    Inventors: Wilma Jean Horkans, Keith T. Kwietniak, Peter S. Locke
  • Patent number: 6471845
    Abstract: A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: October 29, 2002
    Assignees: International Business Machines Corporation, Novellus Systems, Inc.
    Inventors: John O. Dukovic, William E. Corbin, Jr., Erick G. Walton, Peter S. Locke, Panayotis C. Andricacos, James E. Fluegel, Evan Patton, Jonathan Reid
  • Publication number: 20020146903
    Abstract: The present invention relates to a method and apparatus for ensuring uniform and reproducible heating of a deformation-tolerant substrate during low-pressure chemical vapor deposition (CVD) of a metal film on a surface of the substrate. The uniform and reproducible heating of the substrate is achieved in the present invention by positioning the substrate on a beveled surface of a chamfered ring which is located above the heating element in a CVD reactor chamber. The space between heating element, chamfered ring and bottom surface of the substrate define a cavity between the substrate and heating element that ensures that the substrate is heated by radiative means rather than direct contact.
    Type: Application
    Filed: April 10, 2001
    Publication date: October 10, 2002
    Applicant: International Business Machines Corporation
    Inventors: Peter S. Locke, Sandra Guy Malhotra, Fenton Read McFeely, Andrew Herbert Simon, John Jacob Yurkas
  • Patent number: 6413854
    Abstract: A method for forming a structure. A first dielectric material is deposited on a substrate. The first dielectric material is patterned. At least one metal is deposited in and on the first dielectric material. Portions of the at least one metal are removed at least in a region above an upper surface of the first dielectric material. The first dielectric material is removed. A second dielectric material is provided in place of first dielectric material.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: July 2, 2002
    Assignee: International Business Machines Corp.
    Inventors: Cyprian E. Uzoh, Daniel C. Edelstein, Cheryl Faltermeier, Peter S. Locke
  • Publication number: 20020081842
    Abstract: A semiconductor structure, having a semiconductor dielectric material having an opening. A first material lining the opening, the first material comprising MXY, where M is selected from the group consisting of cobalt and nickel, X is selected from the group consisting of tungsten and silicon and Y is selected from the group consisting of phosphorus and boron and a second material filling the lined dielectric material.
    Type: Application
    Filed: April 14, 2000
    Publication date: June 27, 2002
    Inventors: Carlos J. Sambucetti, Steven H. Boettcher, Peter S. Locke, Judith M. Rubino, Soon-Cheon Seo
  • Publication number: 20020066673
    Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.
    Type: Application
    Filed: January 22, 2002
    Publication date: June 6, 2002
    Applicant: International Business Machines Corporation
    Inventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke
  • Patent number: 6368484
    Abstract: A method is described for electroplating a metal structure in a feature formed in a substrate. A seed layer of the metal is deposited on the top surface and on the bottom and sidewalls of the feature. The seed layer is then selectively removed from the top surface, so that only a portion of the seed layer remains in the feature on at least the bottom thereof. The metal is then electroplated using this portion of the seed layer, so that the metal fills the feature. The removal of the seed layer from the top surface causes no electroplating to occur on the top surface.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: April 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Richard P. Volant, Peter S. Locke, Kevin S. Petrarca, David M. Rockwell, Seshadri Subbanna
  • Publication number: 20020027082
    Abstract: A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.
    Type: Application
    Filed: October 23, 2001
    Publication date: March 7, 2002
    Inventors: Panayotis C. Andricacos, W. Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Cyprian E. Uzoh
  • Patent number: 6344129
    Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: February 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Jr., Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke
  • Patent number: 6344125
    Abstract: A process for the electrolytic deposition of a metal, preferably copper or an alloy of copper, directly onto a barrier layer coated on a dielectric layer. The process is advantageous because it electrolytically deposits metal in a pattern that is either the duplicate of a first conductive pattern under the dielectric or the inverse image of the first conductive pattern, depending on the first conductive pattern shape. Thus, metal is deposited on the barrier layer duplicating a first conductive pattern under the dielectric layer when the first pattern is a serpentine pattern and the metal deposits in the spaces between the conductive lines of a first conductive pattern of a discrete passive element such as a spiral.
    Type: Grant
    Filed: April 6, 2000
    Date of Patent: February 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter S. Locke, Kevin S. Petrarca, Seshadri Subbanna, Richard P. Volant
  • Patent number: 6333120
    Abstract: Copper is plated onto a substrate by plating a layer of copper onto the substrate to provide a maximum thickness of about 350 nanometers, followed by subjecting the copper coated substrate to an oxygen containing gaseous ambient in order to roughen the copper surface. Next, a second layer of copper is electroplated onto the structure to provide the desired thickness. The texture of the second layer of copper is independent of the underlayer of copper and has a random or at least substantially random texture.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: December 25, 2001
    Assignee: International Business Machines Corporation
    Inventors: Patrick William DeHaven, Peter S. Locke, Kenneth P Rodbell, Cyprian Emeka Uzoh
  • Patent number: 6331237
    Abstract: A method of reducing etching of a seed layer by a plating solution. Prior to introducing the semiconductor wafer with the seed layer into the plating solution, the etching power of the plating solution is diminished.
    Type: Grant
    Filed: September 1, 1999
    Date of Patent: December 18, 2001
    Assignee: International Business Machines Corporation
    Inventors: Panayotis C. Andricacos, W. Jean Horkans, Keith T. Kwietniak, Peter S. Locke, Cyprian E. Uzoh