Patents by Inventor Peter Sean Feeley

Peter Sean Feeley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446197
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
  • Patent number: 10430116
    Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Singidi, Sampath Ratnam, Renato C. Padilla, Jr., Gary F. Besinga, Peter Sean Feeley
  • Publication number: 20190295660
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Reddy Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Patent number: 10365854
    Abstract: A variety of applications can include apparatus and/or methods that include tracking data temperatures of logical block addresses for a memory device by operating multiple accumulators by one or more data temperature analyzers to count host writes to ranges of logical block addresses. Data temperature for data written by a host is a measure of how frequently data at a logical block address is overwritten. In various embodiments, tracking can include staggering the start of counting by each of the multiple accumulators to provide subsequent binning of logical block addresses bands into temperature zones, which can achieve better data segregation. Data having a logical block address received from a host can be routed to a block associated with a temperature zone based on the binning provided by the staggered operation of the multiple accumulators by one or more data temperature analyzers. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: July 30, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Peter Sean Feeley, Ashutosh Malshe, Sampath Ratnam, Harish Singidi, Vamsi Pavan Rayaprolu
  • Patent number: 10354732
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Thomson, Harish Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Patent number: 10347344
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ashutosh Malshe, Kishore Kumar Muchherla, Harish Singidi, Peter Sean Feeley, Sampath Ratnam, Kulachet Tanpairoj, Ting Luo
  • Publication number: 20190122705
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Reddy Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
  • Publication number: 20190065108
    Abstract: Devices and techniques for correcting for power loss in NAND memory devices are disclosed herein. The NAND memory devices may comprise a number of physical pages. For example, a memory controller may detect a power loss indicator at the NAND flash memory. The memory controller may identify a last-written physical page and determine whether the last-written physical page comprises more than a threshold number of low-read-margin cells. If the last-written physical page comprises more than the threshold number of low-read-margin cells, the memory controller may provide a programming voltage to at least the low-read-margin cells.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Michael G. Miller, Kishore Kumar Muchherla, Harish Singidi, Sampath Ratnam, Renan Padilla, Gary F. Besinga, Peter Sean Feeley
  • Publication number: 20190066739
    Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus that include a memory device having read levels that can be calibrated. A calibration controller implemented with the memory device can trigger a read level calibration based on inputs from one or more trackers monitoring parameters associated with the memory device and a determination of an occurrence of at least one event from a set of events related to the monitored parameters. The monitored parameters can include parameters related to a selected time interval and measurements of read, erase, or write operations of the memory device. Additional apparatus, systems, and methods are disclosed.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Kishore Kumar Muchherla, Ashutosh Malshe, Harish Singidi, Gianni Stephen Alsasua, Gary F. Besinga, Sampath Ratnam, Peter Sean Feeley
  • Publication number: 20190066802
    Abstract: Devices and techniques for read voltage calibration of a flash-based storage system based on host IO operations are disclosed. In an example, a memory device includes a NAND memory array having groups of multiple blocks of memory cells, and a memory controller to optimize voltage calibration for reads of the memory array. In an example, the optimization technique includes monitoring read operations occurring to a respective block, identifying a condition to trigger a read level calibration based on the read operations, and performing the read level calibration for the respective block or a memory component that includes the respective block. In a further example, the calibration is performed based on a threshold voltage to read the respective block, which may be considered when the threshold voltage to read the respective block is evaluated within a sampling operation performed by the read level calibration.
    Type: Application
    Filed: August 29, 2017
    Publication date: February 28, 2019
    Inventors: Ashutosh Malshe, Kishore Kumar Muchhert, Harish Singidi, Peter Sean Feeley, Sampath Ratnam, kulachet Tanpairoj, Ting Luo
  • Publication number: 20190066792
    Abstract: Devices and techniques for NAND temperature data management are disclosed herein. A command to write data to a NAND component in the NAND device is received at a NAND controller of the NAND device. A temperature corresponding to the NAND component is obtained in response to receiving the command. The command is then executed to write data to the NAND component and to write a representation of the temperature. The data is written to a user portion and the representation of the temperature is written to a management portion that is accessible only to the controller and segregated from the user portion.
    Type: Application
    Filed: August 30, 2017
    Publication date: February 28, 2019
    Inventors: Kishore Kumar Muchherla, Sampath Ratnam, Preston Thomson, Harish Singidi, Jung Sheng Hoei, Peter Sean Feeley, Jianmin Huang
  • Publication number: 20160086641
    Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 24, 2016
    Inventors: Koji Sakui, Peter Sean Feeley
  • Patent number: 9208833
    Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: December 8, 2015
    Assignee: Micron Technology
    Inventors: Koji Sakui, Peter Sean Feeley
  • Publication number: 20150333001
    Abstract: Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Koji Sakui, Peter Sean Feeley, Akira Goda
  • Patent number: 9171625
    Abstract: Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 27, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Sean Feeley
  • Patent number: 9093152
    Abstract: Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: July 28, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Sean Feeley, Akira Goda
  • Publication number: 20140313839
    Abstract: Some embodiments include apparatuses and methods for activating a signal associated with an access line coupled to different groups of memory cells during a memory operation of a device, and for sensing data lines of the device during different time intervals of the memory operation to determine the value of information stored in the memory cells. Each of the data lines can be coupled to a respective memory cell of each of the groups of memory cells. In at least one of such apparatuses and methods, the signal applied to the access line can remain activated during the memory operation.
    Type: Application
    Filed: April 23, 2013
    Publication date: October 23, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Sean Feeley
  • Publication number: 20140119117
    Abstract: Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines associated with each row of vertical strings. Each data line associated with a row is coupled to at least one of the vertical strings in the row. Additional apparatuses and methods are described.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Sean Feeley, Akira Goda
  • Patent number: 8713385
    Abstract: Various embodiments include methods, apparatus, and systems to scan at least a portion of a memory device for potential errors when a condition for scanning is met. The condition may be dependent on one or more of a number of read operations, a number of write operations, time, and others. Other embodiments including additional methods, apparatus, and systems are disclosed.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: William Henry Radke, Peter Sean Feeley, Siamack Nemazie
  • Publication number: 20140036590
    Abstract: Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
    Type: Application
    Filed: August 1, 2012
    Publication date: February 6, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Peter Sean Feeley, Koji Sakui, Akira Goda