Abstract: A host integrated circuit is provided with an interrupt aggregator having a signal terminal for coupling to the signal end of an R-2R resistor ladder that has a plurality of rungs corresponding to a plurality of peripheral devices. The interrupt aggregator is configured to process a voltage signal received at the signal terminal to identify any of the peripheral device that intend to trigger an interrupt to a processor.

Abstract: A method, device, and non-transitory computer readable medium that dynamically allocates cache resources includes monitoring a hit or miss rate of a service level objective for each of a plurality of prior workloads and a performance of each of a plurality of cache storage resources. At least one configuration for the cache storage resources for one or more current workloads is determined based at least on a service level objective for each of the current workloads, the monitored hit or miss rate for each of the plurality of prior workloads and the monitored performance of each of the plurality of cache storage resources. The cache storage resources are dynamically partitioned among each of the current workloads based on the determined configuration.

Abstract: A method, device, and non-transitory computer readable medium that dynamically allocates cache resources includes monitoring a hit or miss rate of a service level objective for each of a plurality of prior workloads and a performance of each of a plurality of cache storage resources. At least one configuration for the cache storage resources for one or more current workloads is determined based at least on a service level objective for each of the current workloads, the monitored hit or miss rate for each of the plurality of prior workloads and the monitored performance of each of the plurality of cache storage resources. The cache storage resources are dynamically partitioned among each of the current workloads based on the determined configuration.

Abstract: According to a novel mechanism, each processing device (e.g., a central processing unit (CPU) in a multi-processor system) is assigned to process a single execution thread for a task and the execution thread is processed across various layers of the multi-processor system (such as a network layer and application layer) without being divided into separate threads. Advantageously, upon initialization of the multi-processor system, network context data structures are created equal to the number of processing devices in the system. As used herein, a network context is a logical entity to which zero or more connections are bound during their lifetime. Rather than sharing data structures among execution threads, a multi-processor system allocates memory resources per each network context during initialization of the system. As a result, an execution thread processing a task queued to a particular network context accesses memory resources allocated for that network context only.

Abstract: A broadband tuner includes a tracking filter with calibration to compensate for component errors and drift. The filters use off-die inductors that are preferably within a system-in-package (SIP) with other critical tuner components, which produces a highly integrated tuner front end with high Q filters within a single package. High voltage varactors with a large tuning range can be used for variable capacitors. The integration of the tuner into a SIP allows the tuner design to be optimized for cost and performance while keeping the critical RF layout requirements within the tuner. A configurable tuner front end enables modes for low noise, high linearity, good input return loss (S11) across the entire RF band, and applying a test tone in the calibration mode. The switchable mode enables the tuner to be effective during weak terrestrial reception, strong terrestrial reception, and connection to a cable plant.

Abstract: In-phase (I) and quadrature-phase (Q) signals are corrected for both amplitude and phase imbalances by passing the I and Q signals successively through a first amplitude correction stage, a sum-difference stage, and a second amplitude correction stage. The first amplitude correction stage balances the signal levels of the I and Q signals. The sum-difference stage produce a sum of the input I and Q signals, and a difference of the input I and Q signals, resulting in ideal quadrature in the outputs produced. The second amplitude correction stage corrects the amplitude differences from the sum-difference stage. Circuit configurations are used that minimize errors produced by the signal processing stages.

Abstract: A broadband tuner includes a tracking filter with calibration to compensate for component errors and drift. The filters use off-die inductors that are preferably within a system-in-package (SIP) with other critical tuner components, which produces a highly integrated tuner front end with high Q filters within a single package. High voltage varactors with a large tuning range can be used for variable capacitors. The integration of the tuner into a SIP allows the tuner design to be optimized for cost and performance while keeping the critical RF layout requirements within the tuner. A configurable tuner front end enables modes for low noise, high linearity, good input return loss (S11) across the entire RF band, and applying a test tone in the calibration mode. The switchable mode enables the tuner to be effective during weak terrestrial reception, strong terrestrial reception, and connection to a cable plant.

Abstract: A harmonic suppression mixer for down converting an RF signal to a complex I and Q baseband signal that uses a plurality of switching mixers each with a gain stage to produce a sinusoidal weighted sum of the mixer outputs. Odd harmonics output by each switching mixer is suppressed in the composite signal. A low skew local oscillator (LO) clock generator creates multiple LO phases and drives the mixers. The mixer can be used in low noise direct conversion RF tuners. The mixer is configurable by programming gain stage coefficient values to achieve a variable number of effective mixers used in combination. At low tuning frequencies, all available mixers are programmed with unique coefficients and driven by different LO clock phases to achieve maximum harmonic suppression. At high tuning frequencies, some mixers are paralleled and duplicate coefficients are programmed or mixers are disabled to reduce the number of effective mixers.

Abstract: A harmonic suppression mixer for down converting an RF signal to a complex I and Q baseband signal that uses a plurality of switching mixers each with a gain stage to produce a sinusoidal weighted sum of the mixer outputs. Odd harmonics output by each switching mixer is suppressed in the composite signal. A low skew local oscillator (LO) clock generator creates multiple LO phases and drives the mixers. The mixer can be used in low noise direct conversion RF tuners. The mixer is configurable by programming gain stage coefficient values to achieve a variable number of effective mixers used in combination. At low tuning frequencies, all available mixers are programmed with unique coefficients and driven by different LO clock phases to achieve maximum harmonic suppression. At high tuning frequencies, some mixers are paralleled and duplicate coefficients are programmed or mixers are disabled to reduce the number of effective mixers.

Abstract: A tuner uses a bank of tracking filters to preselect a channel to be received. Each tracking filter covers a range of frequencies. The tracking filters are tunable in frequency using switched capacitors and are tunable in gain by using switched resistors. The switched resistors can be controlled by an automatic gain control circuit that monitors the selected signal and adjust the tracking filter gain to achieve a desired signal level. A switch directs the received signal or signal from a test tone generator into the tracking filters. The test tone, generated by a frequency agile circuit, can be used to calibrate the filters, both in frequency and gain.

Abstract: A local oscillator (LO) generator for driving a bank of mixers that provides precise phase relationship between multi-phase LO outputs comprises a shift register using slave-master-slave flip-flop elements. The LO generator can be used over a wide operating frequency range. The LO generator is suitable for driving a multi-phase LO clock input to a harmonic suppression mixer. A pattern generator produces a pattern signal and a reclocking signal that determines the frequency of the LO signals and the phase delay between the LO output phases.

Abstract: Tuners with high input impedance are connected to a common radio frequency (RF) signal source. A termination load external to the tuners provides matched impedance loading for the transmission line or cable driving the tuners. Alternatively, the termination load can be located inside one tuner with a switch to enable or disable the load. All tuners receive the same signal and no signal degradation is caused when connecting multiple tuners. The multiple tuner connection is useful in television signal receiving devices that receive more than one independent channel, such as digital video recorders or picture-in-picture television receivers.

Abstract: A harmonic suppression mixer for down converting an RF signal to a complex I and Q baseband signal that uses a plurality of switching mixers each with a gain stage to produce a sinusoidal weighted sum of the mixer outputs. Odd harmonics output by each switching mixer is suppressed in the composite signal. A low skew local oscillator (LO) clock generator creates multiple LO phases and drives the mixers. The mixer can be used in low noise direct conversion RF tuners. The mixer is configurable by programming gain stage coefficient values to achieve a variable number of effective mixers used in combination. At low tuning frequencies, all available mixers are programmed with unique coefficients and driven by different LO clock phases to achieve maximum harmonic suppression. At high tuning frequencies, some mixers are paralleled and duplicate coefficients are programmed or mixers are disabled to reduce the number of effective mixers.

Abstract: Techniques are disclosed for compensating for second-order distortion in a wireless communication device. In a zero-intermediate frequency (IF) or low-IF architecture, IM2 distortion generated by the mixer (20) results in undesirable distortion levels in the baseband output signal. A compensation circuit (104) provides a measure of the IM2 distortion current independent of the radio frequency (RF) pathway to generate an IM2 calibration current. The IM2 calibration current is combined with the baseband output signal to thereby eliminate the IM2 currents generated within the RF pathway. In one embodiment, the calibration is provided at the factory during final testing. In alternative embodiment, additional circuitry (156, 158) may be added to the wireless communication device to provide a pathway between the transmitter (150) and the receiver (146). The transmitter signal is provided to the receiver to permit automatic calibration of the unit.