Abstract: A passive vector modulator (PVM) includes a divider that splits an input signal into a first divided signal and a second divided signal 90° apart in phase. The PVM includes a switched transformer phase shifter including primary windings to form first primary windings and second primary windings receiving the first divided signal and the second divided signal respectively. First secondary windings are coupled to the first primary windings, the first secondary windings being center-tapped and outputting first and second phase shifted output signals, phase shifted 180° and 0° respectively. Second secondary windings are coupled to the second primary windings, the second secondary windings being center-tapped and outputting third and fourth phase shifted signals, phase shifted 270° and 90° respectively. The PVM includes a switch configured to receive the phase shifted output signals. The switch selectively outputs one of the phase shifted output signals, or a combination, from the PVM.

Abstract: Systems and methods for enhancing anomaly detection using a pattern dictionary are disclosed. An example method includes receiving, from a wearable device, physiological data of the user, and parsing the physiological data into a set of parsed phrases having a number of parsed phrases by applying a pattern dictionary encoder using a pattern dictionary. Each parsed phrase represents a respective subsequence of the physiological data. The example method includes determining a codelength corresponding to the physiological data based on the set of parsed phrases, and comparing (i) the number of parsed phrases to a parsed phrase threshold, and (ii) the codelength to a codelength threshold using an anomaly detection model. Responsive to the number of parsed phrases exceeding the parsed phrase threshold or the codelength exceeding the codelength threshold, the example method includes generating an alert for display on a user interface indicating that the physiological data is anomalous.

Abstract: A passive vector modulator (PVM) includes a divider that splits an input signal into a first divided signal and a second divided signal 90° apart in phase. The PVM includes a switched transformer phase shifter including primary windings to form first primary windings and second primary windings receiving the first divided signal and the second divided signal respectively. First secondary windings are coupled to the first primary windings, the first secondary windings being center-tapped and outputting first and second phase shifted output signals, phase shifted 180° and 0° respectively. Second secondary windings are coupled to the second primary windings, the second secondary windings being center-tapped and outputting third and fourth phase shifted signals, phase shifted 270° and 90° respectively. The PVM includes a switch configured to receive the phase shifted output signals. The switch selectively outputs one of the phase shifted output signals, or a combination, from the PVM.

Abstract: A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.

Abstract: A virtual core management system including a first physical core and a second physical core, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a first temperature sensor configured to sense a temperature of the first physical core and a second temperature sensor configured to sense a temperature of the second physical core, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the temperature of the first physical core and the temperature of the second physical core.

Abstract: A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.

Abstract: A virtual core management system including a first physical core having a first utilization constraint, a second physical core having a second utilization constraint, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a utilization indicator configured to measure a utilization of the first physical core with respect to the first utilization constraint and measure a utilization of the second physical core with respect to the second utilization constraint, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the utilization of the first physical core and the utilization of the second physical core.

Abstract: Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data.

Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

Abstract: The present disclosure provides methods and systems adapted for use with a processor having one or more physical cores. The methods and systems include a virtual core management component adapted to map one or more virtual cores to at least one of the physical cores to enable execution of one or more programs by the at least one physical core. The one or more virtual cores include one or more logical states associated with the execution of the one or more programs. The methods and systems may include a memory component adapted to store the one or more virtual cores. The virtual core management component may be adapted to transfer the one or more virtual cores from the memory component to the at least one physical core.

Abstract: A virtual core management system including one or more physical cores and one or more virtual cores. Each virtual core respectively includes a collection of logical states associated with execution of a corresponding program. The virtual core management system further includes one or more interrupt controllers configured to send one or more interrupt signals to interrupt execution of a corresponding program associated with at least one of the one or more virtual cores, and a virtual core management component configured to map the at least one virtual core to one of the one or more physical cores and route the one or more interrupt signals to the corresponding physical core.

Abstract: Prediction of data values to be read from memory by a microprocessor for load operations. In one aspect, a method for predicting a data value that will result from a load operation to be executed by the microprocessor includes accessing an entry in a load value prediction table that stores a predicted data value corresponding to the load operation. The predicted data value is stored in a physical storage destination of the microprocessor to be available as a result of the load operation without waiting for execution of the load operation to complete. The storage destination is the destination for a loaded data value resulting from executing the load operation.

Abstract: Software hints embedded in branch instructions direct selection of one of a plurality of branch predictors to use when processing the branch instructions, leading to improved branch prediction (i.e. fewer mis-predictions) over conventional schemes. A software agent assembles branch instructions having associated respective branch predictor control fields compatible with a branch predictor selector and a plurality of branch predictors. Each branch predictor control field is used to perform branch predictor selection, branch predictor control, or both. Branch predictor selection enables selective branch prediction according to an appropriate one of the branch predictors as determined by the software agent by examining context surrounding the branch instruction. Branch predictor control enables control of operation of one or more of the branch predictors.

Abstract: Reducing power consumption in microprocessors for the processing of common values. Common values provided in at least one received operation are encoded into encoded common values having a lower number of bits than the common values prior to encoding. In one aspect, a separate encoding bus is used to provide the encoded common values in various processing of additional received operations in the microprocessor instead of a full-bit bus of the microprocessor, the encoding bus having less bits than the full-bit bus. In another aspect, a result of the operation is predicted based on at least one encoded common value and execution of the operation is bypassed.

Abstract: Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags during atomic trace renaming in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is stored when an atomic trace is renamed. An action that updates flags updates all entries in the table corresponding to younger atomic traces. If the atomic trace is aborted, then the corresponding flag checkpoint is used for restoration of flag state.

Abstract: Managing speculative execution via groups of actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flags at trace boundaries. Flag restoration from checkpoints for trace aborts uses a flag checkpoint table to store flag checkpoints, each corresponding to an atomic trace. The table is accessed for flag restoration in response to a trace abort. In a first technique, a corresponding flag checkpoint is stored in response to trace renaming, and the flag checkpoints are updated as flags are modified. Flags are restored from the flag checkpoint corresponding to an aborted atomic trace. In a second technique, a corresponding flag checkpoint is allocated to an invalid state in response to trace renaming, and initialized on-demand when flags are first modified in accordance with the atomic trace. Flags are restored from the oldest flag checkpoint starting from an aborted atomic trace.

Abstract: Managing speculative execution via groups of one or more actions corresponding to atomic traces enables efficient processing of flag-related actions, as atomic traces advantageously enable single checkpoints of flag values at atomic trace boundaries. Checkpointing flags on-demand for atomic traces in a processor system uses a flag checkpoint table to store a plurality of flag checkpoints, each corresponding to an atomic trace. The table is selectively accessed to provide flag information to restore speculative flags when an atomic trace is aborted. A corresponding flag checkpoint is allocated to an invalid state when an atomic trace is renamed. An action that updates flags initializes the corresponding flag checkpoint (if invalid). If the atomic trace is aborted, then the table is searched according to program order starting with the entry corresponding to the aborted atomic trace. The first (if any) valid checkpoint found is used for flag restoration.

Abstract: Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.

Abstract: A software agent assembles prefetch hint instructions or prefixes defined in an instruction set architecture, the instructions/prefixes conveying prefetch hint information to a processor enabled to execute instructions according to the instruction set architecture. The prefetch hints are directed to control operation of one or more hardware memory prefetcher units included in the processor, providing for increased efficiency in memory prefetching operations. The hints may optionally provide any combination of parameters describing a memory reference traffic pattern to search for, when to begin searching, when to terminate prefetching, and how aggressively to prefetch. Thus the hardware prefetchers are enabled to make improved traffic prediction, providing more accurate results using reduced hardware resources. The hints may include any combination of specific pattern hints (one/two/N-dimensional strides, indirect, and indirect-stride), modifiers including sparse and region, and a prefetch-stop directive.