Patents by Inventor Peter V. Wright

Peter V. Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10453765
    Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
  • Patent number: 10418297
    Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 17, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
  • Publication number: 20190013255
    Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.
    Type: Application
    Filed: May 30, 2018
    Publication date: January 10, 2019
    Inventors: Julio C. Costa, Merrill Albert Hatcher, JR., Peter V. Wright, Jon Chadwick
  • Publication number: 20190013254
    Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.
    Type: Application
    Filed: May 30, 2018
    Publication date: January 10, 2019
    Inventors: Julio C. Costa, Merrill Albert Hatcher, JR., Peter V. Wright, Jon Chadwick
  • Publication number: 20180374846
    Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 27, 2018
    Inventors: Peter V. Wright, Timothy S. Henderson
  • Patent number: 10109623
    Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: October 23, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Peter V. Wright, Timothy S. Henderson
  • Publication number: 20180182903
    Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.
    Type: Application
    Filed: February 21, 2018
    Publication date: June 28, 2018
    Inventors: Peter V. Wright, Timothy S. Henderson
  • Patent number: 9972425
    Abstract: A frequency-dependent resistor and circuitry employing the same are provided. In some embodiments, a resistor includes a substrate, an input port, an output port, and a conductive trace on the substrate between the input port and the output port. A resistance between the input port and the output port for a low frequency signal is at least five times lower than the resistance between the input port and the output port for an RF signal and the ratio of the frequencies of the RF signal to the low frequency signal is at least fifty. Circuitry including a transistor adapted to selectively couple the input to the output in response to a control signal provided via a resistor with resistance for a low frequency signal at least five times lower than resistance for an RF signal will have a reduced switching time while still isolating the RF signal.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: May 15, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Peter V. Wright, Kerry Burger
  • Patent number: 9882019
    Abstract: The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base layer arranged in a first plurality of parallel fingers directly onto the collector layer, and depositing a second base layer arranged in a second plurality of parallel fingers that are interleaved with the first plurality of parallel fingers directly onto the collector layer.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: January 30, 2018
    Assignee: Qorvo US, Inc.
    Inventor: Peter V. Wright
  • Patent number: 9590669
    Abstract: Embodiments include semiconductor devices related to compound varactor circuits. Specifically, a semiconductor device may be constructed of a modified anti-series string of varactor pairs, wherein one varactor in a varactor pair has an effective area larger than the other varactor. Varactor pairs in the anti-series string are arranged such that adjacent varactors coupling varactor pairs have equal effective areas. In some embodiments, the anti-series string may have four varactors (two varactor pairs.) In other embodiments, the anti-series string may have eight varactors (four varactor pairs) or twelve varactors (six varactor pairs). The compound varactor using the modified anti-series string of varactor pairs may be advantageous in reducing second harmonics related to parasitic capacitances in anti-series varactor applications.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: March 7, 2017
    Assignee: Qorvo US, Inc.
    Inventor: Peter V. Wright
  • Publication number: 20170004909
    Abstract: A frequency-dependent resistor and circuitry employing the same are provided. In some embodiments, a resistor includes a substrate, an input port, an output port, and a conductive trace on the substrate between the input port and the output port. A resistance between the input port and the output port for a low frequency signal is at least five times lower than the resistance between the input port and the output port for an RF signal and the ratio of the frequencies of the RF signal to the low frequency signal is at least fifty. Circuitry including a transistor adapted to selectively couple the input to the output in response to a control signal provided via a resistor with resistance for a low frequency signal at least five times lower than resistance for an RF signal will have a reduced switching time while still isolating the RF signal.
    Type: Application
    Filed: November 19, 2015
    Publication date: January 5, 2017
    Inventors: Peter V. Wright, Kerry Burger
  • Publication number: 20160365427
    Abstract: The present disclosure provides a method for fabricating a compound varactor. The method includes steps of depositing a collector layer, depositing a first base layer arranged in a first plurality of parallel fingers directly onto the collector layer, and depositing a second base layer arranged in a second plurality of parallel fingers that are interleaved with the first plurality of parallel fingers directly onto the collector layer.
    Type: Application
    Filed: August 24, 2016
    Publication date: December 15, 2016
    Inventor: Peter V. Wright
  • Publication number: 20160329918
    Abstract: Embodiments include semiconductor devices related to compound varactor circuits. Specifically, a semiconductor device may be constructed of a modified anti-series string of varactor pairs, wherein one varactor in a varactor pair has an effective area larger than the other varactor. Varactor pairs in the anti-series string are arranged such that adjacent varactors coupling varactor pairs have equal effective areas. In some embodiments, the anti-series string may have four varactors (two varactor pairs.) In other embodiments, the anti-series string may have eight varactors (four varactor pairs) or twelve varactors (six varactor pairs). The compound varactor using the modified anti-series string of varactor pairs may be advantageous in reducing second harmonics related to parasitic capacitances in anti-series varactor applications.
    Type: Application
    Filed: January 25, 2016
    Publication date: November 10, 2016
    Inventor: Peter V. Wright
  • Patent number: 9484471
    Abstract: Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 1, 2016
    Assignee: Qorvo US, Inc.
    Inventor: Peter V. Wright
  • Patent number: 9455357
    Abstract: Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: September 27, 2016
    Assignee: Qorvo US, Inc.
    Inventor: Peter V. Wright
  • Publication number: 20160247800
    Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 25, 2016
    Inventors: Peter V. Wright, Timothy S. Henderson
  • Publication number: 20160133758
    Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common and may be electrically coupled to form a parallel varactor pair. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common. The parallel varactor pair may be advantageous in reducing die area for compound varactor circuits.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Inventor: Peter V. Wright
  • Publication number: 20160079444
    Abstract: Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventor: Peter V. Wright
  • Patent number: 9203362
    Abstract: Embodiments include but are not limited to apparatuses and systems including a quadrature lattice matching network including first path having a series inductor and a shunt inductor, and a second path having a series capacitor and a shunt capacitor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: December 1, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventor: Peter V. Wright
  • Publication number: 20150325573
    Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 12, 2015
    Applicant: TriQuint Semiconductor, Inc.
    Inventors: Peter V. Wright, Timothy S. Henderson