Patents by Inventor Peter V. Wright
Peter V. Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881833Abstract: An integrated passive die includes a substrate, an input node, an output node, and RF filtering circuitry. The RF filtering circuitry includes a number of LC tank circuits coupled between the input node and the output node. Each one of the LC tank circuits include an inductor and a capacitor. The inductor is formed by a metal trace over the substrate. The capacitor is coupled in parallel with the inductor over the substrate. The inductor and the capacitor are provided such that a resonance frequency of the combination of the inductor and the capacitor is less than a self-resonance frequency of the inductor.Type: GrantFiled: October 18, 2022Date of Patent: January 23, 2024Assignee: Qorvo US, Inc.Inventor: Peter V. Wright
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Patent number: 11742819Abstract: Apparatus and methods are provided for coupling RF signals. A lattice coupler design incorporating a pair of shunt inductors provides (i) a virtual ground for biasing and (ii) improved performance characteristics, in both splitter and combiner configurations. Magnetic coupling between the shunt inductors can be selected to maintain improved performance characteristics over a wide bandwidth, while retaining compactness and high efficiency. A design procedure, variations, and results are disclosed.Type: GrantFiled: May 17, 2022Date of Patent: August 29, 2023Inventor: Peter V. Wright
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Publication number: 20230058725Abstract: An integrated passive die includes a substrate, an input node, an output node, and RF filtering circuitry. The RF filtering circuitry includes a number of LC tank circuits coupled between the input node and the output node. Each one of the LC tank circuits include an inductor and a capacitor. The inductor is formed by a metal trace over the substrate. The capacitor is coupled in parallel with the inductor over the substrate. The inductor and the capacitor are provided such that a resonance frequency of the combination of the inductor and the capacitor is less than a self-resonance frequency of the inductor.Type: ApplicationFiled: October 18, 2022Publication date: February 23, 2023Inventor: Peter V. Wright
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Patent number: 11489506Abstract: An integrated passive die includes a substrate, an input node, an output node, and RF filtering circuitry. The RF filtering circuitry includes a number of LC tank circuits coupled between the input node and the output node. Each one of the LC tank circuits include an inductor and a capacitor. The inductor is formed by a metal trace over the substrate. The capacitor is coupled in parallel with the inductor over the substrate. The inductor and the capacitor are provided such that a resonance frequency of the combination of the inductor and the capacitor is less than a self-resonance frequency of the inductor.Type: GrantFiled: October 23, 2020Date of Patent: November 1, 2022Assignee: Qorvo US, Inc.Inventor: Peter V. Wright
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Publication number: 20210126607Abstract: An integrated passive die includes a substrate, an input node, an output node, and RF filtering circuitry. The RF filtering circuitry includes a number of LC tank circuits coupled between the input node and the output node. Each one of the LC tank circuits include an inductor and a capacitor. The inductor is formed by a metal trace over the substrate. The capacitor is coupled in parallel with the inductor over the substrate. The inductor and the capacitor are provided such that a resonance frequency of the combination of the inductor and the capacitor is less than a self-resonance frequency of the inductor.Type: ApplicationFiled: October 23, 2020Publication date: April 29, 2021Inventor: Peter V. Wright
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Publication number: 20210126620Abstract: Radio frequency (RF) filtering circuitry includes an input node, an output node, a shunt node, a first bulk acoustic wave (BAW) resonator, a second BAW resonator, a first inductor, and a second inductor. The first BAW resonator is coupled between the input node and the output node. The second BAW resonator is coupled between an intermediate node and the shunt node. The first inductor is coupled between the input node and the intermediate node. The second inductor is coupled between the output node and the intermediate node.Type: ApplicationFiled: October 23, 2020Publication date: April 29, 2021Inventor: Peter V. Wright
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Patent number: 10833071Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.Type: GrantFiled: August 2, 2018Date of Patent: November 10, 2020Assignee: Qorvo US, Inc.Inventors: Peter V. Wright, Timothy S. Henderson
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Patent number: 10755992Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.Type: GrantFiled: May 30, 2018Date of Patent: August 25, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
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Patent number: 10658259Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.Type: GrantFiled: May 30, 2018Date of Patent: May 19, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
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Patent number: 10622271Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.Type: GrantFiled: May 30, 2018Date of Patent: April 14, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
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Patent number: 10586747Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.Type: GrantFiled: May 30, 2018Date of Patent: March 10, 2020Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
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Patent number: 10535784Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.Type: GrantFiled: February 21, 2018Date of Patent: January 14, 2020Assignee: Qorvo US, Inc.Inventors: Peter V. Wright, Timothy S. Henderson
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Patent number: 10490471Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.Type: GrantFiled: May 30, 2018Date of Patent: November 26, 2019Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
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Patent number: 10453765Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.Type: GrantFiled: May 30, 2018Date of Patent: October 22, 2019Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
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Patent number: 10418297Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.Type: GrantFiled: May 30, 2018Date of Patent: September 17, 2019Assignee: Qorvo US, Inc.Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
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Publication number: 20190013255Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.Type: ApplicationFiled: May 30, 2018Publication date: January 10, 2019Inventors: Julio C. Costa, Merrill Albert Hatcher, JR., Peter V. Wright, Jon Chadwick
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Publication number: 20190013254Abstract: The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.Type: ApplicationFiled: May 30, 2018Publication date: January 10, 2019Inventors: Julio C. Costa, Merrill Albert Hatcher, JR., Peter V. Wright, Jon Chadwick
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Publication number: 20180374846Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.Type: ApplicationFiled: August 2, 2018Publication date: December 27, 2018Inventors: Peter V. Wright, Timothy S. Henderson
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Patent number: 10109623Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.Type: GrantFiled: April 29, 2016Date of Patent: October 23, 2018Assignee: Qorvo US, Inc.Inventors: Peter V. Wright, Timothy S. Henderson
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Publication number: 20180182903Abstract: Embodiments include apparatuses and methods related to vertically stacked varactors. Specifically two varactors may be constructed of vertically stacked layers including an anode layer, a contact layer, and a varactor layer. The two varactors may share one or more layers in common. In some embodiments the two varactors may share the anode layer in common, while in other embodiments the two varactors may share the contact layer in common.Type: ApplicationFiled: February 21, 2018Publication date: June 28, 2018Inventors: Peter V. Wright, Timothy S. Henderson