Patents by Inventor Peter Weigand

Peter Weigand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5963837
    Abstract: A method for planarizing a semiconductor structure having a first surface region with a high aspect ratio topography and a second surface region with a low aspect ratio topography. A flowable material is deposited over the first and second surface regions of the structure. A portion of the material fills gaps in the high aspect ratio topography to form a substantially planar surface over the high aspect ratio topography. A doped layer, for example phosphorus doped glass, is formed over the flowable oxide material. The doped layer is disposed over the high aspect ratio and over the low aspect ratio regions. Upper surface portions over the low aspect ratio region are higher than an upper surface of the flowable material. The upper portion of the doped layer is removed over both the first and second surface portions to form a layer with a substantially planar surface above both the high aspect ratio region and the low aspect ratio region.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: October 5, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Matthias Ilg, Dirk Tobben, Peter Weigand
  • Patent number: 5937541
    Abstract: Apparatus and method are provided for obtaining improved measurement and control of the temperature of a semiconductor wafer (W) during processing. The apparatus includes a chuck for holding a wafer during processing, a coolant gas supply (16), and a temperature sensing arrangement for measuring and controlling the temperature of the wafer during processing. A top face of the chuck (22) over which the wafer is positioned, is configured with a plurality of holes (34) into which the coolant gas, such as helium, is admitted at controlled rate and pressure. The coolant gas passes through a narrow space (36) between the top face of the chuck and the underside of the wafer and is evacuated via an exhaust line (30) after being heated to (or nearly to) the temperature of the wafer. Temperature of the now-heated coolant gas is continuously measured by a temperature sensor arrangement which generates a signal controlling the pressure and flow of coolant gas to the wafer.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: August 17, 1999
    Assignees: Siemens Aktiengesellschaft, Kabushiki Kaisha Toshiba
    Inventors: Peter Weigand, Naohiro Shoda
  • Patent number: 5926716
    Abstract: A method for forming a microstructure includes photolithographically forming a vertically extending post on a portion of a surface of a substrate to provide a first structure. A flowable, sacrificial material is deposited over a surface of the first structure. The flowable, sacrificial materially flows off the top surface and sidewall portions of the post onto adjacent portions of the surface of the substrate to provide a second structure. A non-sacrificial material is deposited over a surface of the second structure. The non-sacrificial material is deposited to conform to the surface of the second structure. The non-sacrificial is deposited over the sacrificial material, over the sidewall portions and over the top surface of the post. The deposited sacrificial material is selectively removed while the non-sacrificial material remains to form a third structure with a horizontal member provided by the non-sacrificial material.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: July 20, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Dirk Tobben, Peter Weigand
  • Patent number: 5899736
    Abstract: A method for fabricating an electrically blowable fuse on a semiconductor substrate. The method includes forming a fuse portion 102 on the semiconductor substrate. The fuse portion is configured to turn substantially non-conductive when a current exceeding a predefined current level passes through the fuse portion. The method also includes depositing a substantially conformal first layer 302 of dielectric material above the fuse portion and depositing a second layer 304 of dielectric material above the first layer, thereby forming a protrusion of dielectric material above the fuse portion. The second layer being different from the first layer. The method further includes performing chemical-mechanical polish on the protrusion to form an opening through the second layer above the protrusion. There is also included etching, in a substantially isotropic manner, a portion of the first layer through the opening to form a microcavity 502 about the fuse portion.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: May 4, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Peter Weigand, Dirk Tobben
  • Patent number: 5854126
    Abstract: A method for forming a plurality of electrically conductive wires on a substrate. The method includes forming a relatively non-planar metal layer over a surface of the substrate. A self-planarizing material is deposited over the metal layer. The self-planarizing material forms a planarization layer over the surface of the metal layer. The planarization layer has a surface relatively planar compared to the relatively non-planar metal layer. A photoresist layer is deposited over the surface of the planarization layer. The photoresist layer is patterned with a plurality of grooves to form a mask with such grooves exposing underling portions of the planarization layer. The photoresist mask is used as a mask to etch grooves in the exposed portions of the planarization layer and thereby form a second mask. The second mask exposes underling portions of the relatively non-planar metal layer.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: December 29, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventors: Dirk Tobben, Bruno Spuler, Martin Gutsche, Peter Weigand
  • Patent number: 5851899
    Abstract: Described is a method for filling shallow trench isolation (STI) trenches in a semiconductor substrate of an integrated circuit with an insulating material and planarizing the resulting structure to the level of adjacent portions of the integrated circuit. The method comprises forming trenches in the non-active regions of a semiconductor substrate, depositing a layer of oxide in the trenches and over the surface of the semiconductor substrate, and removing the oxide from the active areas of the integrated circuit structure, leaving oxide-filled shallow trench isolation structures having a substantially planar topography with respect to the rest of the integrated circuit structure.
    Type: Grant
    Filed: August 8, 1996
    Date of Patent: December 22, 1998
    Assignee: Siemens Aktiengesellschaft
    Inventor: Peter Weigand
  • Patent number: 4952108
    Abstract: The invention relates to an apparatus for automatically feeding each of a sequence of crucibles (3), which are arranged on a conveyor, to a test oven (12) for vaporization and content analysis of a sample contained in each crucible. For cradling each crucible, a gripper head (13) is provided. In order to provide an apparatus in which the number of mechanically moving parts is minimized, the gripper head is rigidly mounted on the end of an operating piston (7). The gripper head preferably comprises two spaced, co-linear crosspieces (16) which face each other and engage under an outwardly extending circumferential flange (17) on the top of each crucible (3). The operating piston (7) and a lifting piston (6) are oriented vertically and connected together at their tops by a transverse crossbar (10). Lifting piston (6) is rotated about its axis (8) by a drive motor, thereby revolving operating piston (7) along a circle (11).
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: August 28, 1990
    Assignee: Foss Heraeus Analysensysteme GmbH
    Inventors: Peter Weigand, Harald Langen, Hans J. Kupka, Gerhard Rossel, Walter Weigand, Rudiger Wittenbeck, Karl-Heinz Hessler