Abstract: A system may have a support structure that separates an exterior region from an interior region. The system may include a lighting system with interior and/or exterior lights with adjustable diffusers. An interior light may be used as a task light, a cabin light, a sensor indicator light, or a trim light. Adjustments to the adjustable diffusers can be used to adjust the angular spread of emitted light for operation in different lighting modes.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

Abstract: A method is provided for constructing a microelectronic assembly. A semiconductor substrate having a MEMS device formed on a first portion thereof, a semiconductor device formed on a second portion thereof, and a build up layer having a first portion formed over the MEMS device and a second portion formed over the semiconductor device is provided. The first portion of the build up layer over the MEMS device is removed. A release body is formed adjacent to the MEMS device. A structural material is formed over the release body. An opening is formed in the structural material to expose the release body. The release body is removed through the opening to form a cavity between the MEMS device and the structural material. The opening in the structural material is sealed with a sealing material.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A semiconductor fabrication process includes forming a gate dielectric layer (120) overlying a substrate (101) that includes a III-V semiconductor compound. The gate dielectric layer is patterned to produce a gate dielectric structure (121) that has a substantially vertical sidewall (127), e.g., a slope of approximately 45° to 90°. A metal contact structure (130) is formed overlying the wafer substrate. The contact structure is laterally displaced from the gate dielectric structure sufficiently to define a gap (133) between the two. The wafer (100) is heat treated, which causes migration of at least one of the metal elements to form an alloy region (137) in the underlying wafer substrate. The alloy region underlies the contact structure and extends across all or a portion of the wafer substrate underlying the gap. An insulative or dielectric capping layer (140,150) is then formed overlying the wafer and covering the portion of the substrate exposed by the gap.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A magnetic nanoparticle (22), a magnetic nanomaterial (30), assembly (30), and a method for synthsising a magnetic nanoparticle, relating to thermodynamically stable and air stable ferromagnetic nanoparticles of adjustable aspect ratio made upon decomposition of organometallic precursors in solution in the presence of a reaction gas and a mixture of organic ligands. The magnetic nanomaterial comprises magnetic nanoparticles of homogeneous size, shape, and magnetic orientation that comprises a magnetic core (24, 34) ferromagnetic at room temperature and/or operating temperatures, and a non-magnetic matrix (26, 36) encapsulating the magnetic core. This magnetic nanomaterial could be used in high frequency integrated circuit applications, such as used in wireless portable electronic devices, to enchance magnetic field confinement and improve passive component performance at MHz and GHz frequency in a variety of passive and active devices, such as transformers, on-chip signal isolation, inductors, and the like.

Abstract: Semiconductor devices (300, 400, and 500) including an integrated circuit (IC) device (100) coupled to a micro-electro-mechanical systems (MEMS) device (200) and a method (600) for producing same are disclosed. The IC device includes a die seal ring (130) and the MEMS device includes a MEMS seal ring (230), and the IC device is coupled to the MEMS device via the die seal ring and the MEMS seal ring. The MEMS device may include one or more passive devices (450, 475) coupled to it. Moreover, a substrate (510) including an aperture (550) may be coupled to the passive device, wherein the aperture enables the passive device to be trimmed after being disposed on the MEMS device. The semiconductor devices include an RF signal path (486) and at least one other signal path (482 and 484), wherein the other signal path(s) may be an analog and/or a digital signal path.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form atop electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A method is provided for constructing a microelectronic assembly. A semiconductor substrate having a MEMS device formed on a first portion thereof, a semiconductor device formed on a second portion thereof, and a build up layer having a first portion formed over the MEMS device and a second portion formed over the semiconductor device is provided. The first portion of the build up layer over the MEMS device is removed. A release body is formed adjacent to the MEMS device. A structural material is formed over the release body. An opening is formed in the structural material to expose the release body. The release body is removed through the opening to form a cavity between the MEMS device and the structural material. The opening in the structural material is sealed with a sealing material.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form atop electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: A magnetic nanoparticle (22), a magnetic nanomaterial (30), assembly (30), and a method for synthsising a magnetic nanoparticle, relating to thermodynamically stable and air stable ferromagnetic nanoparticles of adjustable aspect ratio made upon decomposition of organometallic precursors in solution in the presence of a reaction gas and a mixture of organic ligands. The magnetic nanomaterial comprises magnetic nanoparticles of homogeneous size, shape, and magnetic orientation that comprises a magnetic core (24, 34) ferromagnetic at room temerature and/or operating temperatures, and a non-magnetic matrix (26, 36) encapsulating the magnetic core. This magenetic nanomaterial could be used in high frequency integrated circuit applications, such as used in wireless portable electronic devices, to enchance magnetic field confienment and improve passive component performance at MHz and GHz frequency in a variety of passive and active devices, such as transformers, on-chip signal isolation, inductors, and the like.

Abstract: A method of making a semiconductor device includes the steps of: providing a semiconductor substrate (110, 510, 1010, 1610) having a patterned interconnect layer (120, 520, 1020, 1620) formed thereon; depositing a first dielectric material (130, 530, 1030, 1630) over the interconnect layer; depositing a first electrode material (140, 540, 1040, 1640) over the first dielectric material; depositing a second dielectric material (150, 550, 1050, 1650) over the first electrode material; depositing a second electrode material (160, 560, 1060, 1660) over the second dielectric material; patterning the second electrode material to form a top electrode (211, 611, 1111, 1611) of a first capacitor (210, 710, 1310, 1615); and patterning the first electrode material to form a top electrode (221, 721, 1221, 1621) of a second capacitor (220, 720, 1320, 1625), to form an electrode (212, 712, 1212, 1612) of the first capacitor, and to define a resistor (230, 730, 1330).

Abstract: An electromechanical resonator includes a substrate (150, 450), an anchor (110, 510, 810) coupled to the substrate, a beam (120, 620, 1020, 1120, 1220, 1420) coupled to the anchor and suspended over the substrate, and a drive electrode (130, 435, 630, 930, 933, 935, 1030, 1035, 1130, 1135, 1435) coupled to the substrate and separated from the beam by a gap (140, 445, 640, 1040, 1045, 1140, 1145, 1445). The beam has a first surface (321, 621, 1021, 1121), a second surface (322, 622), and a third surface (323, 623, 1023, 1123, 1223, 1423). The first surface defines a width and a height, the second surface defines the height and a length, and the third surface defines the length and the width. The width, height, and length are substantially mutually perpendicular, and the beam resonates substantially only in compression mode and substantially only along an axis defined by the length.

Abstract: An electromechanical resonator includes a substrate (150, 450), an anchor (110, 510, 810) coupled to the substrate, a beam (120, 620, 1020, 1120, 1220, 1420) coupled to the anchor and suspended over the substrate, and a drive electrode (130, 435, 630, 930, 933, 935, 1030, 1035, 1130, 1135, 1435) coupled to the substrate and separated from the beam by a gap (140, 445, 640, 1040, 1045, 1140, 1145, 1445). The beam has a first surface (321, 621, 1021, 1121), a second surface (322, 622), and a third surface (323, 623, 1023, 1123, 1223, 1423). The first surface defines a width and a height, the second surface defines the height and a length, and the third surface defines the length and the width. The width, height, and length are substantially mutually perpendicular, and the beam resonates substantially only in compression mode and substantially only along an axis defined by the length.

Abstract: A semiconductor device and a method of making a semiconductor device. A damascene metal layer (16) is formed in an insulating dielectric layer (12), which is in direct electrical communication with a substrate (10). A layer of a passive element, such as first capacitor electrode layer (20) is disposed on metal layer (16) and preferably is offset relative to metal layer (16) to allow a direct electrical interconnect through a via (36) to metal layer (16). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor (28) and optionally a second resistor (32). In yet another embodiment, metal layer (16) is a damascene copper layer.

Abstract: A semiconductor device and a method of making a semiconductor device. A damascene metal layer (16) is formed in an insulating dielectric layer (12), which is in direct electrical communication with a substrate (10). A layer of a passive element, such as first capacitor electrode layer (20) is disposed on metal layer (16) and preferably is offset relative to metal layer (16) to allow a direct electrical interconnect through a via (36) to metal layer (16). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor (28) and optionally a second resistor (32). In yet another embodiment, metal layer (16) is a damascene copper layer.

Abstract: A semiconductor device and a method of making a semiconductor device. A damascene metal layer (16) is formed in an insulating dielectric layer (12), which is in direct electrical communication with a substrate (10). A layer of a passive element, such as first capacitor electrode layer (20) is disposed on metal layer (16) and preferably is offset relative to metal layer (16) to allow a direct electrical interconnect through a via (36) to metal layer (16). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor (28) and optionally a second resistor (32). In yet another embodiment, metal layer (16) is a damascene copper layer.