Abstract: Method for forming a semiconductor device having an capacitor, where the capacitor is in-laid in a cavity formed in the semiconductor substrate and part of a high density memory. One embodiment first forms a bottom electrode in the cavity and then fills the cavity with a sacrificial layer to allow chemical mechanical polishing (CMP) of at least one of the capacitor electrodes. After removing portions of the bottom electrode and portions of the sacrificial layer, a dielectric layer is formed. A top electrode is then formed over the dielectric layer. The dielectric layer so formed isolates the bottom electrode from the top electrode preventing shorting and leakage currents. In one embodiment, a single top electrode layer is formed for multiple bottom electrodes, reducing the complexity of the memory circuit.

Abstract: A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

Abstract: A method and apparatus for simulating the design of a ferroelectric circuit uses a processor (501). The processor (501) executes a simulator (540) from memory (538) to exercise a ferroelectric model (544). The ferroelectric model (544) keeps track of turning points or extrema points (FIGS. 11-17) in a history data file (542). This history data in file (542) is then used with eqs. 3-11 herein to curve model between voltage/charge history points from the file (542) and a current operating voltage/charge point of the ferroelectric device. This curve modeling effectively and efficiently determines the charge stored in a ferroelectric capacitor (FIGS. 7 or 8) as voltage across the ferroelectric capacitor is varied over time and temperature. History data points are selectively removed from the data file (542) to maintain and enable time-efficient determination of charge (Q) in the ferroelectric device over time.

Abstract: A method for forming an embedded DRAM structure along with tungsten plugged MOS transistor devices begins by forming capacitor tungsten plugs (46) and bit-line tungsten plugs (44). A bottom capacitor electrode (48b) is formed to protect the tungsten plug (46). Simultaneously, an optionally-removable barrier region (48a) is formed to protect the plug (44). A capacitor dielectric (52) is deposited and oxygen annealed to form a ferroelectric capacitor material. The barrier (48a) and the lower electrode (48b) protect all of the tungsten plugs (46 and 44) from being adversely oxidized by the oxygen anneal. A top electrode (54 and 56) of the ferroelectric capacitor is then deposited, lithographically patterned, and etched. The lithographic patterning and etching of the top electrode may also be further utilized to remove the barrier region (48a).

Abstract: A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.