Abstract: A sensor device coupled to a communication interface bus, the sensor device includes: a current source having a first terminal operable to receive a supply current, a second terminal operable to provide a supply current, and a control terminal, wherein an operating voltage is supplied by a current through the current source; a voltage clamp having a first terminal coupled to the second terminal of the current source, a second terminal coupled to a power supply terminal, and an output terminal operable to provide a current sense signal; and a control circuit having an input terminal coupled to the output terminal of the voltage clamp and an output terminal coupled to the control terminal of the current source operable to provide an adjustment signal responsive to the current sense signal, wherein the current source is configured to adjust the current through the current source responsive to the adjustment signal.

Abstract: Embodiments include a primary short circuit coupled to a primary side of a transformer and a dampening element, coupled to a transducer coupled to a secondary side of the transformer, configured to dampen a received signal during a portion of a reverberation period.

Abstract: Embodiments include a primary short circuit (PSC) coupled to a primary side of a transformer and a dampening element, coupled to a transducer coupled to a secondary side of the transformer, configured to dampen a received signal during a portion of a reverberation period. The PSC and the dampening element may be activated substantially simultaneously. Activation of the PSC circuit mitigates a parallel resonance otherwise arising, in part, in the transducer, but, increases the received signal by a DC shift voltage. The dampening element dampens the DC shift voltage. The received signal may be dampened prior to amplification of the received signal by an amplifier. The dampening facilitates earlier and more precise measurement, during the reverberation period, of at least one operating characteristic for the PAS sensor. Another embodiment prevents the DC shift voltage by selectively activating the PSC within a determined time of a zero-crossing of a given signal.

Abstract: A sensor device coupled to a communication interface bus, the sensor device enters a low power mode in which some operations of the sensor device are suspended when the sensor device receives insufficient power over the bus, thereby significantly reducing the likelihood that digital components of the sensor device will need to be reset due to an under-voltage condition.

Abstract: A sensor device coupled to a communication interface bus, the sensor device includes: a current source having a first terminal operable to receive a supply current, a second terminal operable to provide a supply current, and a control terminal, wherein an operating voltage is supplied by a current through the current source; a voltage clamp having a first terminal coupled to the second terminal of the current source, a second terminal coupled to a power supply terminal, and an output terminal operable to provide a current sense signal; and a control circuit having an input terminal coupled to the output terminal of the voltage clamp and an output terminal coupled to the control terminal of the current source operable to provide an adjustment signal responsive to the current sense signal, wherein the current source is configured to adjust the current through the current source responsive to the adjustment signal.

Abstract: A sensor device coupled to a communication interface bus, the sensor device enters a low power mode in which some operations of the sensor device are suspended when the sensor device receives insufficient power over the bus, thereby significantly reducing the likelihood that digital components of the sensor device will need to be reset due to an under-voltage condition.

Abstract: Embodiments include a primary short circuit (PSC) coupled to a primary side of a transformer and a dampening element, coupled to a transducer coupled to a secondary side of the transformer, configured to dampen a received signal during a portion of a reverberation period. The PSC and the dampening element may be activated substantially simultaneously. Activation of the PSC circuit mitigates a parallel resonance otherwise arising, in part, in the transducer, but, increases the received signal by a DC shift voltage. The dampening element dampens the DC shift voltage. The received signal may be dampened prior to amplification of the received signal by an amplifier. The dampening facilitates earlier and more precise measurement, during the reverberation period, of at least one operating characteristic for the PAS sensor. Another embodiment prevents the DC shift voltage by selectively activating the PSC within a determined time of a zero-crossing of a given signal.

Abstract: A method includes configuring a transmitter to provide at least three output levels used to form an output signal. The method further includes adjusting a duration of at least one of the output levels to control an average value of the output signal independently of an amplitude of a first harmonic of the output signal.

Abstract: A method includes configuring a transmitter to provide at least three output levels used to form an output signal. The method further includes adjusting a duration of at least one of the output levels to control an average value of the output signal independently of an amplitude of a first harmonic of the output signal.

Abstract: In an embodiment, an LED controller is configured to form a charge transfer sequence to selectively enable LED transistors of a plurality of LED transistors that are configured for coupling in parallel with a plurality of LEDs. An embodiment may include that the LED controller is configured to sequentially couple a charge capacitor to a gate-to-source capacitor of each LED transistor of the plurality of LED transistors to one of charge or to refresh the gate-to-source capacitor of a respective LED transistor and to one of enable or re-enable the respective LED transistor wherein the gate-to-source capacitor is a parasitic gate-to-source capacitor of the LED transistor wherein the charge capacitor is sequentially coupled to the gate-to-source capacitor of each LED transistor.

Abstract: In an embodiment, an LED controller is configured to form a charge transfer sequence to selectively enable LED transistors of a plurality of LED transistors that are configured for coupling in parallel with a plurality of LEDs. An embodiment may include that the LED controller is configured to sequentially couple a charge capacitor to a gate-to-source capacitor of each LED transistor of the plurality of LED transistors to one of charge or to refresh the gate-to-source capacitor of a respective LED transistor and to one of enable or re-enable the respective LED transistor wherein the gate-to-source capacitor is a parasitic gate-to-source capacitor of the LED transistor wherein the charge capacitor is sequentially coupled to the gate-to-source capacitor of each LED transistor.

Abstract: In one embodiment, a closed loop control system is caused to operate in an open loop configuration. At some time while operating in the open loop configuration the system detected the presence or absence of a.c. signals in an output signal of the system in order to detect the presence or absence of a failure of a control loop element, such as an output capacitor.

Abstract: A protection circuit for protecting an electronic circuit against EMC disturbances and/or negative transient overvoltage pulses comprises a switch in series between a power supply and the electronic circuit to be protected; a comparator for comparing a first operating parameter with a second operating parameter and producing a comparison signal, the comparison signal being used as a control signal for controlling opening and closing of the switch; and a delay circuit adapted for delaying closing of the switch. A corresponding method is also provided.

Abstract: An output driver circuit has an input, an output node, and first and second transistors coupled in series between the output node and a first source of operating potential. Parasitic diodes of the first and second transistors are anti-serially coupled. The output driver circuit has first and second control circuits coupled to control the first and second transistors respectively. The first transistor is controlled as a controlled current source depending on a signal at the input during normal conditions when the current that flows through the output is in a first direction, and the second control circuit controls the second transistor to prevent unwanted DC current at the output from flowing through the output in a second direction. The first and second transistors are also controlled to limit unwanted transient currents during an EMC disturbance substantially symmetrically.

Abstract: In one embodiment, a closed loop control system is caused to operate in an open loop configuration. At some time while operating in the open loop configuration the system detected the presence or absence of a.c. signals in an output signal of the system in order to detect the presence or absence of a failure of a control loop element, such as an output capacitor.

Abstract: A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design.

Abstract: A switching circuit that transitions using a switch transistor. During the initial stages of a high-low transition, a control loop provides supplemental pre-charge to the gate of the switch transistor to reduce high-low switching delays. Once the current flowing through the switch transistor rises to a level causing the output voltage to change at specified speed threshold, a loop opening mechanism opens the loop. Further opening of the switch transistor in the high-low transition is taken care of by a relatively constant current source. At that point, no or negligible feedback current is used to charge the gate of the switch transistor. Low-high transitions may be performed in a similar complementary manner.

Abstract: A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design.

Abstract: A protection circuit for protecting an electronic circuit against EMC disturbances and/or negative transient overvoltage pulses comprises a switch in series between a power supply and the electronic circuit to be protected; a comparator for comparing a first operating parameter with a second operating parameter and producing a comparison signal, the comparison signal being used as a control signal for controlling opening and closing of the switch; and a delay circuit adapted for delaying closing of the switch. A corresponding method is also provided.

Abstract: An output driver circuit has an input, an output node, and first and second transistors coupled in series between the output node and a first source of operating potential. Parasitic diodes of the first and second transistors are anti-serially coupled. The output driver circuit has first and second control circuits coupled to control the first and second transistors respectively. The first transistor is controlled as a controlled current source depending on a signal at the input during normal conditions when the current that flows through the output is in a first direction, and the second control circuit controls the second transistor to prevent unwanted DC current at the output from flowing through the output in a second direction. The first and second transistors are also controlled to limit unwanted transient currents during an EMC disturbance substantially symmetrically.