Patents by Inventor Petra Leber
Petra Leber has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10095475Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: GrantFiled: December 13, 2017Date of Patent: October 9, 2018Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20180276548Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.Type: ApplicationFiled: December 29, 2017Publication date: September 27, 2018Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
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Publication number: 20180276545Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.Type: ApplicationFiled: March 21, 2017Publication date: September 27, 2018Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
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Publication number: 20180276547Abstract: In an approach for protecting recoding logic in a computing environment, a processor obtains an operand of an instruction in a first data format. A processor converts the operand from the first data format to a second data format. A processor generates a predicted residue of the operand in the second data format, wherein generating the predicted residue of the operand in the second data format comprises: generating a residue of the operand from the first data format.Type: ApplicationFiled: December 15, 2017Publication date: September 27, 2018Inventors: Steven R. Carlough, Petra Leber, Daniel Lipetz, Silvia M. Mueller
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Publication number: 20180253282Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.Type: ApplicationFiled: May 1, 2018Publication date: September 6, 2018Inventors: Petra LEBER, Cedric LICHTENAU, Silvia M. MUELLER
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Patent number: 10067744Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.Type: GrantFiled: December 8, 2016Date of Patent: September 4, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20180203670Abstract: Processing within a computing environment is facilitated. An operand of an instruction is obtained, which includes decimal floating point data encoded in a compressed format. An operation is performed on the operand absent decompressing a source value of a trailing significand of the decimal floating point data in the compressed format.Type: ApplicationFiled: January 16, 2017Publication date: July 19, 2018Inventors: Steven R. Carlough, Petra Leber, Silvia Melitta Mueller, Kerstin Schelm
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Publication number: 20180165063Abstract: A circuit is provided which includes arithmetic computation logic configured to add or subtract operands of variable length to produce a result in a sign-magnitude data format. The circuit also includes an overflow detector to provide an overflow signal indicative of whether the result fits within a specified result length l. The overflow detector operates on the operands prior to the arithmetic computation logic producing the result to determine, independent of the result produced by the arithmetic computation logic, whether the result fits within the specified result length l.Type: ApplicationFiled: December 8, 2016Publication date: June 14, 2018Inventors: Petra LEBER, Cedric LICHTENAU, Silvia M. MUELLER
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Publication number: 20180101358Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: ApplicationFiled: December 13, 2017Publication date: April 12, 2018Inventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Patent number: 9870200Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: GrantFiled: November 17, 2016Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20170235574Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Publication number: 20170235573Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: ApplicationFiled: May 3, 2017Publication date: August 17, 2017Inventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 9734126Abstract: A system and method for controlling post-silicon configurable instruction behavior are provided. For example, the method includes receiving data related to a compute circuit. The method also includes detecting a data pattern in the data. The method further includes determining that the data pattern is a special case that the compute circuit may handle improperly. The method also includes selecting a value from a post-silicon configurable data set based on the detected data. Further, the method includes changing a behavior of the compute circuit to produce a different output result based on the value selected from the post-silicon configurable data set.Type: GrantFiled: October 10, 2016Date of Patent: August 15, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James R. Cuffney, Nicol Hofmann, Michael Klein, Petra Leber, Cédric Lichtenau, Silvia M. Mueller, Timothy J. Slegel
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Patent number: 9727399Abstract: A residue-based error checking mechanism is provided for checking for error in a shift operation of a shifter. The checking includes: partitioning an input vector into the shifter into one or more bit groups of bit width W; generating a predicted residue on the input vector being shifted, the generating including masking out any bit group of bit width W fully shifted out by the shift operation from contributing to the predicted residue, and the generating accounting for any bits of a bit group of the input vector partially shifted out by the shift operation; generating a result residue on a result vector of the shift operation; and comparing the result residue with the predicted residue to check for an error in the result vector of the shift operation.Type: GrantFiled: September 29, 2016Date of Patent: August 8, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven R. Carlough, Petra Leber, Silvia M. Mueller, Andreas Wagner
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Patent number: 9684514Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: September 10, 2014Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 9684515Abstract: A condition code can depend upon a numerical output of a floating point operation for a processing pipeline. A classification can be determined for the floating point operation of a received instruction. In response to the classification and using condition determination logic, a value can be calculated for the condition code by inferring from data that is available from the processing pipeline before the numerical output is available. The value for the condition code can be provided to branch decision logic of the processing pipeline.Type: GrantFiled: October 15, 2014Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Son T. Dao, Petra Leber, Silvia M. Mueller
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Patent number: 9658828Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: GrantFiled: October 2, 2015Date of Patent: May 23, 2017Assignee: International Business Machines CorporationInventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20170068517Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Inventors: Steven R. Carlough, Klaus M. Kroener, Petra Leber, Cedric Lichtenau, Silvia M. Mueller
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Publication number: 20160098248Abstract: Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.Type: ApplicationFiled: October 2, 2015Publication date: April 7, 2016Inventors: Steven R. CARLOUGH, Klaus M. KROENER, Petra LEBER, Cedric LICHTENAU, Silvia M. MUELLER
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Publication number: 20160098249Abstract: Logic is provided for performing decimal and binary floating point arithmetic calculations on first and second operands. The method includes: receiving the first and second operands in packed format; unpacking the first and second operands; swapping the first operand to a fourth operand and the second operand to a third operand, if an exponent of the first operand is less than an exponent of the second operand, otherwise storing the first operand to the third operand and the second operand to the fourth operand; aligning the third operand and the fourth operands based on the exponent difference of the third and fourth operand and a number of leading zeroes of the third operand; performing an add/subtract operation on the aligned third and fourth operands with normalizing and rounding between the operands; and packing the result obtained from the add/subtract.Type: ApplicationFiled: October 2, 2015Publication date: April 7, 2016Inventors: Steven R. CARLOUGH, Juergen HAESS, Michael KLEIN, Klaus M. KROENER, Petra LEBER, Silvia M. MUELLER, Kerstin SCHELM