Patents by Inventor Phil Park
Phil Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150213856Abstract: A precharge circuit may include a precharge control unit, a first precharge unit, and a second precharge unit. The precharge control unit may generate a read precharge signal and a write precharge signal in response to a read signal, a write signal, and a precharge signal. The first precharge unit may precharge a data input/output line to a first voltage level in response to the read precharge signal. The second precharge unit may precharge the data input/output line to either a second voltage level or a third voltage level in response to the write precharge signal.Type: ApplicationFiled: April 30, 2014Publication date: July 30, 2015Applicant: SK hynix Inc.Inventor: Mun Phil PARK
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Patent number: 8966326Abstract: An error detecting circuit of a semiconductor apparatus, comprising: a fail detecting section configured to receive 2-bit first test data signals outputted from a first block and 2-bit second test data signals outputted from a second block, disable a first fail detection signal when the 2-bit first test data signals have different levels, disable a second fail detection signal when the 2-bit second test data signals have different levels, and disable both the first and second fail detection signals when the 2-bit first test data signals have the same level, the 2-bit second test data signals have the same level, and levels of the 2-bit first test data signals and the 2-bit second test data signals are the same with each other.Type: GrantFiled: February 20, 2013Date of Patent: February 24, 2015Assignee: SK Hynix Inc.Inventors: Kang Youl Lee, Mun Phil Park
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Publication number: 20140185399Abstract: A system for testing a memory device includes a memory device configured to include a plurality of memory cells, receive a test information having a first frequency, access memory cells corresponding to an address included in the test information, and activate a fail signal if fail occurs in the memory cells corresponding to the address, a test device configured to generate a test information having a second frequency different from the first frequency, and a test mediation device configured to generate the test information having the first frequency and the address based on the test information having the second frequency and the fall signal and store the address corresponding to the fail memory cells in response to the fail signal as a fail address.Type: ApplicationFiled: March 16, 2013Publication date: July 3, 2014Applicant: SK HYNIX INC.Inventor: Mun-Phil PARK
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Patent number: 8745740Abstract: The invention relates to an apparatus for detecting malicious sites, comprising: a monitoring unit for monitoring all processes being executed in a computing apparatus; a hook code insertion unit for inserting a hook code in a process executed in a browser when the execution of the browser is detected by the monitoring unit; a danger level determining unit that, upon the detection of a website movement, uses the hook code to inspect a stack structure of a process implemented according to the website movement and determine whether or not to perform the stack structure inspection, and determines whether or not the website to which the movement has been made is a malicious site; and a database for storing a list of sites determined to be malicious.Type: GrantFiled: November 1, 2010Date of Patent: June 3, 2014Assignee: AHNLAB., Inc.Inventors: Ju Hyun Oh, Chang Woo Lee, Chong Phil Park
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Patent number: 8686786Abstract: A semiconductor device includes: a first driving voltage generation unit configured to generate a first driving voltage; a fuse unit coupled between an output node for receiving the first driving voltage and a fuse state sensing node; a driving unit configured to drive the fuse state sensing node with a second driving voltage in response to a control signal; a voltage level control unit configured to generate a voltage level control signal in response to a fuse state sensing signal that corresponds to a voltage level of the fuse state sensing node; and a second driving voltage generation unit configured to control and output a voltage level of the second driving voltage in response to the voltage level control signal. The semiconductor device repeatedly performs a rupture operation by monitoring a fuse state sensing signal.Type: GrantFiled: August 17, 2012Date of Patent: April 1, 2014Assignee: SK Hynix Inc.Inventors: Mun-Phil Park, Jung-Hwan Lee
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Patent number: 8601327Abstract: A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a first input/output strobe signal, a redundancy data inputting/outputting unit configured to input/output data from the redundancy cell block in response to the first input/output strobe signal, and a connection selecting unit configured to selectively connect the normal data inputting/outputting units and the redundancy data inputting/outputting unit to a plurality of local data lines in response to a address.Type: GrantFiled: November 11, 2010Date of Patent: December 3, 2013Assignee: Hynix Semiconductor Inc.Inventor: Mun-Phil Park
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Publication number: 20130257520Abstract: A semiconductor device includes: a first driving voltage generation unit configured to generate a first driving voltage; a fuse unit coupled between an output node for receiving the first driving voltage and a fuse state sensing node; a driving unit configured to drive the fuse state sensing node with a second driving voltage in response to a control signal; a voltage level control unit configured to generate a voltage level control signal in response to a fuse state sensing signal that corresponds to a voltage level of the fuse state sensing node; and a second driving voltage generation unit configured to control and output a voltage level of the second driving voltage in response to the voltage level control signal. The semiconductor device repeatedly performs a rupture operation by monitoring a fuse state sensing signal.Type: ApplicationFiled: August 17, 2012Publication date: October 3, 2013Inventors: Mun-Phil PARK, Jung-Hwan LEE
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Patent number: 8531906Abstract: A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.Type: GrantFiled: January 31, 2013Date of Patent: September 10, 2013Assignee: SK Hynix Inc.Inventors: Kwi-Dong Kim, Mun-Phil Park, Sung-Ho Kim
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Patent number: 8437205Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to a data mask during a data mask operation; and a bit line sense amplifier configured to sense and amplify a voltage difference between the pair of bit lines and electrically couple the pair of bit lines to a pair of segment input/output lines in response to the column control signal.Type: GrantFiled: December 16, 2010Date of Patent: May 7, 2013Assignee: SK Hynix Inc.Inventors: Mun Phil Park, Jung Hwan Lee
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Patent number: 8379473Abstract: A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks.Type: GrantFiled: November 9, 2009Date of Patent: February 19, 2013Assignee: Hynix Semiconductor Inc.Inventors: Kwi-Dong Kim, Mun-Phil Park, Sung-Ho Kim
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Patent number: 8305837Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.Type: GrantFiled: September 23, 2011Date of Patent: November 6, 2012Assignee: Hynix Semiconductor Inc.Inventor: Mun-Phil Park
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Patent number: 8305838Abstract: A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level.Type: GrantFiled: September 23, 2011Date of Patent: November 6, 2012Assignee: Hynix Semiconductor Inc.Inventor: Mun-Phil Park
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Patent number: 8299263Abstract: A new N-heterocyclic catalyst system which contains N-heterocyclic carbene and amido as ligands, which are strongly bound to a palladium metal. Another heteroatom functionality can be used as a third ligand L. The NHC-amidate ligand system is unique in structure, and shows excellent reactivities in a number of chemical reactions. The chemical reactions include carbon-carbon and carbon-heteroatom (oxygen and nitrogen) bond formations, and oxidation reactions of saturated carbon chemicals via C—H activation.Type: GrantFiled: July 30, 2009Date of Patent: October 30, 2012Assignee: University of Southern CaliforniaInventors: Kyung Woon Jung, Kyung Soo Yoo, Satoshi Sakaguchi, Chan Phil Park, Justin O'Neill, Joo Ho Lee
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Patent number: 8300485Abstract: A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.Type: GrantFiled: December 7, 2010Date of Patent: October 30, 2012Assignee: SK Hynix Inc.Inventors: Kyu Nam Lim, Hong Sok Choi, Ki Myung Kyung, Mun Phil Park, Sun Hwa Park
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Publication number: 20120233692Abstract: The invention relates to an apparatus for detecting malicious sites, comprising: a monitoring unit for monitoring all processes being executed in a computing apparatus; a hook code insertion unit for inserting a hook code in a process executed in a browser when the execution of the browser is detected by the monitoring unit; a danger level determining unit that, upon the detection of a website movement, uses the hook code to inspect a stack structure of a process implemented according to the website movement and determine whether or not to perform the stack structure inspection, and determines whether or not the website to which the movement has been made is a malicious site; and a database for storing a list of sites determined to be malicious.Type: ApplicationFiled: November 1, 2010Publication date: September 13, 2012Applicant: AHNLAB., Inc.Inventors: Ju Hyun Oh, Chang Woo Lee, Chong Phil Park
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Patent number: 8233338Abstract: A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test.Type: GrantFiled: June 2, 2010Date of Patent: July 31, 2012Assignee: Hynix Semiconductor Inc.Inventors: Kwi-Dong Kim, Mun-Phil Park, Sung-Ho Kim
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Publication number: 20120106273Abstract: Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus may include: a column control signal generator configured to generate a column control signal for a pair of bit lines corresponding to a data mask during a data mask operation; and a bit line sense amplifier configured to sense and amplify a voltage difference between the pair of bit lines and electrically couple the pair of bit lines to a pair of segment input/output lines in response to the column control signal.Type: ApplicationFiled: December 16, 2010Publication date: May 3, 2012Applicant: Hynix Semiconductor Inc.Inventors: Mun Phil PARK, Jung Hwan Lee
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Publication number: 20120054562Abstract: A semiconductor memory device having a bank including a redundancy cell block and a plurality of normal cell blocks includes a plurality of normal data inputting/outputting units configured to respectively input/output data from the normal cell blocks in response to a first input/output strobe signal, a redundancy data inputting/outputting unit configured to input/output data from the redundancy cell block in response to the first input/output strobe signal, and a connection selecting unit configured to selectively connect the normal data inputting/outputting units and the redundancy data inputting/outputting unit to a plurality of local data lines in response to a address.Type: ApplicationFiled: November 11, 2010Publication date: March 1, 2012Inventor: Mun-Phil PARK
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Patent number: D665727Type: GrantFiled: October 26, 2011Date of Patent: August 21, 2012Assignee: Kumho Tire Co., Inc.Inventors: Jae Moon Lee, Uk Seo, Hae Dong Jung, Chang Jung Park, Jae Phil Park, Christopher T. Baker, Edward P. Cercek, Terry M. Edwards
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Patent number: D726100Type: GrantFiled: February 24, 2014Date of Patent: April 7, 2015Assignee: Kumho Tire Co., Inc.Inventors: Hae-Dong Jeong, Jae-Hyun Han, Tae-Min Kim, Jae-Phil Park, Chang-Jung Park, In-Hee Park, Uk Seo, Sung-Hoon In