Abstract: A semiconductor memory apparatus includes: a cell region having a plurality of unit cells each of which has a switching MOS transistor for transferring data. A peripheral circuit unit accesses data stored in the unit cell. A threshold voltage control unit controls the threshold voltage of the switching MOS transistor.

Abstract: A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal.

Abstract: The present invention relates to a semiconductor memory device with a fixed burst length, including a column control circuit, the semiconductor memory device including: a command decoder decoding external commands to be output as an internal command with fixed burst length information; a column controlling unit giving a bank address to the internal command to be output as a column control signal; and a bank controlling a read and write operation corresponding to the fixed burst length in accordance with on the column control signal.

Abstract: A semiconductor memory device has a timing margin for internal operations. The semiconductor memory device can activate an internal control signal for controlling an external address sooner than an internal control signal for controlling an external command to secure a sufficient time for data access. The semiconductor memory device includes a command decoding circuit configured to decode an external command to output an internal command signal for an internal operation corresponding to the external command, a control circuit configured to generate a strobe signal for controlling the internal operation in response to the internal command signal and an internal address signal by decoding an address signal received from outside such that the internal address signal activates sooner than the strobe signal, and a column decoding circuit configured to generate a data access signal when both the internal address signal and the strobe signal are activated.

Abstract: A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal.

Abstract: A column decoder according includes: a plurality of main decoding units coupled to different memory banks that decode a pre-decoding signal and output column selection signals to the corresponding memory banks; and one or more pre-decoders, having a lesser number than the main decoders, which generates and outputs the pre-decoding signal by decoding the column address and the bank information signal.

Abstract: Disclosed is a semiconductor memory apparatus capable of improving precharge performance. The semiconductor memory apparatus includes a plurality of memory banks, data input/output lines commonly connected to the memory banks, and a plurality of precharge circuit units connected to the data input/output lines and aligned in an extension direction of the data input/output lines while being spaced apart from each other by a predetermined distance.

Abstract: A write driving circuit includes a plurality of driving units that write data corresponding to detection signals on memory banks, and at least one detecting unit that detects data input from the outside, and outputs the detection signals to two or more driving units among the plurality of driving units.

Abstract: In a memory device that operates at high speed, a bit-line sense amplifier driver is provided to overdrive a sense amplifier in a refresh mode. A bit-line sense amplifier driver includes a refresh overdriving control unit that is coupled to an external power supply terminal and a sense amplifier power line signal output terminal, and driven by a refresh flag signal and a sense amplifier power line enable signal to apply an external supply voltage to the sense amplifier power line signal output terminal in a refresh mode. Therefore, it is possible to prevent a driving voltage from serving as noise, which hinders the high speed operation of the memory device.

Abstract: The present invention relates to a semiconductor memory device with a fixed burst length, including a column control circuit, the semiconductor memory device including: a command decoder decoding external commands to be output as an internal command with fixed burst length information; a column controlling unit giving a bank address to the internal command to be output as a column control signal; and a bank controlling a read and write operation corresponding to the fixed burst length in accordance with on the column control signal.

Abstract: A combo semiconductor memory apparatus capable of reducing current and power consumption is provides. The semiconductor memory apparatus includes: a signal generator that generates a voltage control signal according to the level of an external voltage; and a voltage generator that pumps up the level of the external voltage in response to the voltage control signal and outputs the pumped voltage to a high-level voltage output terminal, or supplies the external voltage as a high-level voltage.

Abstract: A semiconductor memory apparatus includes: a cell region having a plurality of unit cells each of which has a switching MOS transistor for transferring data. A peripheral circuit unit accesses data stored in the unit cell. A threshold voltage control unit controls the threshold voltage of the switching MOS transistor.

Abstract: A circuit for controlling a sense amplifier of a semiconductor memory apparatus including a sense amplifier control unit that controls an enable point of a sense amplifier control signal which is generated by an active command and a precharge command, according to whether a refresh signal is enabled. A sense amplifier driver that generates a sense amplifier driving signal in response to input of the sense amplifier control signal and a bit line equalization signal.

Abstract: A semiconductor memory apparatus includes a main bank configured to combine a first sub bank and a second sub bank. A center bitline sense amplifier array is arranged in a region where the first sub bank meets the second sub bank. A first precharge section is arranged above the first sub bank and a second precharge section is arranged below the second sub bank. The first precharge section precharges local input/output lines of the first sub bank and the second sub bank and the second precharge section precharges the local input/output lines.

Abstract: In a memory device that operates at high speed, a bit-line sense amplifier driver is provided to overdrive a sense amplifier in a refresh mode. A bit-line sense amplifier driver includes a refresh overdriving control unit that is coupled to an external power supply terminal and a sense amplifier power line signal output terminal, and driven by a refresh flag signal and a sense amplifier power line enable signal to apply an external supply voltage to the sense amplifier power line signal output terminal in a refresh mode. Therefore, it is possible to prevent a driving voltage from serving as noise, which hinders the high speed operation of the memory device.

Abstract: Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.

Abstract: The present invention discloses a circuit for controlling a pulse width including a frequency detection circuit for extracting an operation frequency band by receiving an external clock, delaying the external clock for a different time and comparing a frequency of the external clock with frequencies of the external clocks delayed for the different time, respectively, and outputting a plurality of mode signals according to the operation frequency band; and a pulse generation circuit for generating a pulse having its width varied by the operation frequency, by using a delay time based on the plurality of mode signals from the frequency detection circuit. As a result, the circuit for controlling the pulse width can be applied to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supporting various operation frequencies.

Abstract: A cartridge having a sensor hole to be opened/closed and a method and an apparatus for driving the same. To improve a problem that a cartridge receiving a DVD-RAM disc which has been once withdrawn therefrom performs the recording process under the same conditions as a bare disc, the disclosed cartridge has a unit for flexibly opening/closing the sensor hole in accordance with a result of a defect check, so that information processing process is greatly accelerated.

Abstract: A cartridge having a sensor hole to be opened/closed and a method and an apparatus for driving the same. To improve a problem that a cartridge receiving a DVD-RAM disc which has been once withdrawn therefrom performs the recording process under the same conditions as a bare disc, the disclosed cartridge has a unit for flexibly opening/closing the sensor hole in accordance with a result of a defect check, so that information processing process is greatly accelerated.