Abstract: A graphics processor is provided. The graphics processor includes a memory storing image data for presentation and a display memory region in communication with the memory, the display memory region supplying image data to a display panel for presentation. The graphics processor includes bandwidth control logic configured to monitor a lag between an output from the display memory region and an input into the display memory region. The bandwidth control logic is further configured to prevent a level of the display memory from decrementing when the lag between the output and the input is capable of causing corruption on the display panel due to a lack of data from the display memory region. A method for avoiding a buffer under run and a device are included.

Abstract: A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included.

Abstract: A hardware implemented method for resizing an image is provided. In this method, the image is captured and a size of the image is calculated as the image is being received by a display controller. Thereafter, a scaling ratio is calculated based on the calculated size of the image and an output image size. The display controller then scales the image according to the calculated scaling ratio. A display controller and a resizer for resizing the image are also described.

Abstract: An interface for a graphics controller enabling communication with a camera module is provided. The interface includes a first port configured to receive serial image data from a camera module and a second port configured to receive a clock signal, wherein the clock signal is utilized to indicate both a horizontal synchronization and a vertical synchronization for frames of image data received from the camera module. An image capture device having the serial interface and methods for reducing a number of signals utilized for an interface receiving image data are also included.

Abstract: A display controller and method for reducing power consumption of an electro-optical image display while still providing a useful display. A source of a set of image data words corresponding to individual pixels of an image is provided. A control circuit is adapted to substitute for a selected subset of the set of image data words the image data words from one or more contiguous pixels and to provide the resulting modified set of image data words to an output port to be made available to the electro-optical image display. The method provides a set of image data words corresponding to individual pixels of an image, substitutes for a selected subset of the set of image data words the image data words from one or more contiguous pixels, and makes available to the electro-optical image display the modified set of data words resulting from the substitution.

Abstract: A method for obtaining an image having a plurality of exposure regions is described. The method includes exposing first and second regions of an image sensor, reading out first image data from the first region, pausing a clock signal to the image sensor after the reading out of the first image data, resuming the clock signal to the imaging module, and reading out second image data from the image sensor for the second region of the image. A graphics controller and imaging device for capturing images having multiple exposure regions are also described.

Abstract: Histogram circuitry is provided to increment a tonal value tally corresponding to received pixel data without immediately writing the incremented tally back to a histogram table within a main memory. Instead, the tonal value and corresponding incremented tonal value tally are stored in a temporary memory of the histogram circuitry. Since received pixel data has a high likelihood of having the same tonal value as recently received pixel data, the tonal value of the received pixel data is first checked for a match with one of the recently received tonal values stored in the temporary memory. If the received tonal value is present in the temporary memory, there is no need to access the histogram table within the main memory to retrieve the corresponding tally. The tally corresponding to the received tonal value can simply be incremented in the temporary memory of the histogram circuitry.

Abstract: An interface for an integrated circuit chip is provided. The interface includes a first port configured to receive a command signal indicating whether command information or data is being transferred to the integrated circuit chip. The interface further includes a second port configured to receive the command information and the data. Coded data detection logic configured to detect a transition of the command signal indicating that the command information and the data are coded is provided. The transition of the command signal occurs subsequent to a first clock cycle indicating a type of access to the integrated circuit. A method for reducing overhead for a serial interface when receiving or transmitting data is also included.

Abstract: A memory for a graphics processor is provided. The memory includes a write first-in-first-out (FIFO) region of the memory for receiving pixel data, and a read FIFO region for accessing the pixel data received into the memory through the write FIFO. The memory has a memory controller having write assembly logic for rearranging the pixel data received by the write FIFO for storage in the memory. The write assembly logic is configured to write data representing a first pixel and a second pixel across a plurality of data segments in the memory, where corresponding bit locations for the data representing the first pixel and the data representing the second pixel are contiguous. A graphics controller having the memory and a method for preventing data corruption from being displayed during an underflow are included.

Abstract: A memory controller that includes a write first in first out (FIFO) region of the memory for receiving pixel data and a read FIFO region of the memory for accessing the pixel data received through the write FIFO is provided. The memory controller is configured to rearrange the pixel data received by the write FIFO for storage in the memory by writing data representing a first pixel and a second pixel across a plurality of registers in the memory, wherein corresponding bit locations for the data representing the first pixel and the data representing the second pixel are stored within a same one of the plurality of registers. The memory controller is configured to grant access to one of multiple requests for access to the memory based on corresponding bit locations associated with the multiple requests. A graphics controller and a method for prioritizing access to a memory are provided.

Abstract: A graphics processor is provided. The graphics processor includes a memory storing image data for presentation and a display memory region in communication with the memory, the display memory region supplying image data to a display panel for presentation. The graphics processor includes bandwidth control logic configured to monitor a lag between an output from the display memory region and an input into the display memory region. The bandwidth control logic is further configured to prevent a level of the display memory from decrementing when the lag between the output and the input is capable of causing corruption on the display panel due to a lack of data from the display memory region. A method for avoiding a buffer under run and a device are included.

Abstract: A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a non-volatile memory for storing a look up table (LUT). The graphics controller further includes a register port. The CPU provides a LUT value to the register port. Look up circuitry, which is in communication with the LUT register port, receives the LUT value from the register port and the LUT circuitry retrieves a corresponding LUT sequence from the LUT. The LUT sequence represents an operation to be performed by the LUT circuitry. The system is further provided with a register block, which can be programmed with values based on the operation to be performed.

Abstract: A preferred embodiment is directed to an image processing device for receiving pixel data provided to the device as follows: it is grouped into frames, each pixel datum has an associated value, and first, second, and third pixel data correspond respectively to first, second, and third frames. The image processing device is adapted for processing the pixel data, and has a low-power motion monitoring mode and a capture mode. Further, the pixel data is preferably provided by a data source external to the device. The image processing device preferably includes a control unit for: (a) receiving the pixel data; (b) summing the values of the first pixel data to produce a first total value for the first frame; (c) summing the values of the second pixel data to produce a second total value for the second frame, and (d) causing the image processing device to process the third pixel data only if the difference between the first and second total values exceeds a threshold.

Abstract: The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the register block to know when to proceed with a requested write operation. The register block has both a write request input and a read request input, each of which is separately actuated to initiate a write operation or read operation, respectively. The cpu/mpu initiates a write operation by actuating the write request input while maintaining the read request input negated. The register block responds to actuation of its write request input by getting ready for initiate the requested write operation, and waiting for a signal letting it know if the requested operation is a valid write operation. If the requested write operation is deemed valid, then the register block executes the requested write operation only upon the negation of the write request.

Abstract: A method for obtaining an image having a plurality of exposure regions is described. The method includes exposing first and second regions of an image sensor, reading out first image data from the first region, pausing a clock signal to the image sensor after the reading out of the first image data, resuming the clock signal to the imaging module, and reading out second image data from the image sensor for the second region of the image. A graphics controller and imaging device for capturing images having multiple exposure regions are also described.

Abstract: A method for converting between color space formats initiates with identifying a first color space format. Then, both an offset parameter and a scale parameter are selected. The offset parameter and the scale parameter are associated with the first color space format. A conversion matrix configured to convert values associated with the first color space format to a second color space format is identified. When to apply the offset parameter and the scale parameter in relation to application of the conversion matrix is determined, i.e., to the input for the conversion matrix or to the output from the conversion matrix. A computer readable medium, a display controller and an integrated circuit are also included.

Abstract: A method for generating a long exposure image is described. The method includes receiving image data for a plurality of images and adding the image data to a frame buffer. For each of the images, image data corresponding to a long exposure region is added to the frame buffer by adding a color value for each pixel from the image data to a corresponding color value of a corresponding pixel stored in the frame buffer, and storing the sum in the frame buffer. A device for generating long exposure images is also described.

Abstract: The invention is directed to apparatus, methods, and systems for calculating parameters from particular pixel components of first and second frames, and triggering a function pertaining to the image processing of a later-created frame if a particular difference between the two parameters is detected. In one embodiment, the present invention is directed to a method for triggering a processing function for a frame of image data. The method includes: (a) calculating a first parameter from pixels of a first region of a first frame; (b) calculating a second parameter from pixels of a corresponding second region of a second frame; (c) comparing the first parameter with the second parameter; and (d) triggering a function if a particular difference between the first and second parameters is detected. The calculating of the first parameter includes summing at least one particular component of the pixels of the first region.

Abstract: A system for configuring a chip to perform certain operations is provided. The system includes a CPU. The CPU is in communication with a graphics controller. The graphics controller includes a non-volatile memory for storing a look up table (LUT). The graphics controller further includes a register port. The CPU provides a LUT value to the register port. Look up circuitry, which is in communication with the LUT register port, receives the LUT value from the register port and the LUT circuitry retrieves a corresponding LUT sequence from the LUT. The LUT sequence represents an operation to be performed by the LUT circuitry. The system is further provided with a register block, which can be programmed with values based on the operation to be performed.

Abstract: A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor processor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface.