Abstract: The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the register block to know when to proceed with a requested write operation. The register block has both a write request input and a read request input, each of which is separately actuated to initiate a write operation or read operation, respectively. The cpu/mpu initiates a write operation by actuating the write request input while maintaining the read request input negated. The register block responds to actuation of its write request input by getting ready for initiate the requested write operation, and waiting for a signal letting it know if the requested operation is a valid write operation. If the requested write operation is deemed valid, then the register block executes the requested write operation only upon the negation of the write request.

Abstract: A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured to store addresses associated with the external device. The address space provides an address section. The address section is associated with the external device and is subdivided into address sub-sections associated with an address range and assigned through the chip select signal. The address sub-sections are configured to determine a bus cycle based on an association with either the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states. A device and a method for optimizing a bus cycle length between a CPU and an external device in communication with the CPU are provided.

Abstract: Histogram circuitry is provided to increment a tonal value tally corresponding to received pixel data without immediately writing the incremented tally back to a histogram table within a main memory. Instead, the tonal value and corresponding incremented tonal value tally are stored in a temporary memory of the histogram circuitry. Since received pixel data has a high likelihood of having the same tonal value as recently received pixel data, the tonal value of the received pixel data is first checked for a match with one of the recently received tonal values stored in the temporary memory. If the received tonal value is present in the temporary memory, there is no need to access the histogram table within the main memory to retrieve the corresponding tally. The tally corresponding to the received tonal value can simply be incremented in the temporary memory of the histogram circuitry.

Abstract: A central processing unit (CPU) configured to apply an intelligent wait methodology is provided. The CPU includes a chip select module that defines a chip select signal associated with an external device. The chip select module includes an address space configured to store addresses associated with the external device. The address space provides an address section. The address section is associated with the external device and is subdivided into address sub-sections associated with an address range and assigned through the chip select signal. The address sub-sections are configured to determine a bus cycle based on an association with either the CPU monitoring a wait line between the CPU and the external device or the CPU waiting for a number of wait states. A device and a method for optimizing a bus cycle length between a CPU and an external device in communication with the CPU are provided.

Abstract: A method and associated apparatus is provided for displaying a live image in a display window without corruption or loss of image data. More specifically, the method and associated apparatus maintain consistency between a size of an image to be displayed and a size of a display window in which the image is to be displayed. The method requires implementation of dimension value changes associated with the image to be displayed and the display window to be delayed until all required dimension value changes have been stored in a memory. Upon completion of storing each required dimension value change in the memory, a size change completion signal is provided by setting an enable bit within the memory. Upon receipt of a trigger signal while the enable bit is set, the dimension value changes associated with the image to be displayed and the display window are implemented together.

Abstract: A display controller and method for reducing power consumption of an electro-optical image display while still providing a useful display. A source of a set of image data words corresponding to individual pixels of an image is provided. A control circuit is adapted to substitute for a selected subset of the set of image data words the image data words from one or more contiguous pixels and to provide the resulting modified set of image data words to an output port to be made available to the electro-optical image display. The method provides a set of image data words corresponding to individual pixels of an image, substitutes for a selected subset of the set of image data words the image data words from one or more contiguous pixels, and makes available to the electro-optical image display the modified set of data words resulting from the substitution.

Abstract: A display controller configured to communicate with a microprocessor is provided. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. A bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is included. The bus interface is configured to communicate with a set of command signals. The set of command signals defines both whether read operations and write operations are to occur over a bus cycle and whether valid data exists for each bit of the read operation and the write operation. Each command signal in the set of command signals defines enable data for the read operations or write operations. A system including the display controller and methods for adapting the display controller to communicate with a variety of microprocessors are also included.

Abstract: A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface.

Abstract: Broadly speaking, an image overlay apparatus and corresponding method of operation are provided. More specifically, the image overlay apparatus and corresponding method of operation combine multiple sets of display data in an efficient manner while eliminating storage of additional display data in a display memory. Key data is written to the display memory to define a portion of the viewable area of the display component that will be used for rendering an incoming set of display data. The key data is modified using appropriate portions of the incoming set of display data. Modification of the key data using the incoming set of display data can be performed during residence of the key data in the display memory or during transmission of the key data to a display component.

Abstract: A method for enhancing storage capability for a display controller initiates with receiving video display data having a color format associated with a first sub-sampling scheme. Then, a size associated with the video display data is adjusted. Next, the video display data is compressed through a second sub-sampling scheme. Then, the compressed data having the color format is stored. A computer readable medium, a display controller and a digital video device are also provided as environments in which the method can be stored and/or implemented.

Abstract: A memory controller includes logic for requesting a read operation from memory and logic for generating an address for the read operation. The memory controller also includes logic for storing both, data associated with the address and data associated with a consecutive address in temporary storage. Logic for determining if a request for data associated with a next read operation is for the data associated with the consecutive address in the temporary storage is also provided. A method for optimizing memory bandwidth, a device and an integrated circuit are also provided.

Abstract: A display controller configured to communicate with a microprocessor is provided. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. A bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is included. The bus interface is configured to communicate with a set of command signals. The set of command signals defines both whether read operations and write operations are to occur over a bus cycle and whether valid data exists for each bit of the read operation and the write operation. Each command signal in the set of command signals defines enable data for the read operations or write operations. A system including the display controller and methods for adapting the display controller to communicate with a variety of microprocessors are also included.

Abstract: A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller operates at a first clock speed and microprocessor operates at a second clock speed. The display controller includes a memory core for storing image data to be displayed and a register set containing configuration data enabling presentation of the image data. An asynchronous bus interface enabling communication over a bus between the memory core of the display controller and the microprocessor is also included. The asynchronous bus interface is configured to be independent of the second clock speed of the microprocessor and a difference between the first clock speed and the second clock speed. Flip flop chain redundancy circuitry is included in the bus interface.