Abstract: A modular multi-turbine unit of fixed toroidal support structures having a rail system designed to allow each of the plurality of turbines to rotate to a most efficient position relative to the wind for generating power, a computer control system capable of positioning each of the plurality of turbines to most effectively generate power from the wind, preventing damage to the turbines, and providing a wind predictive model based on the wind characteristics for the area in which the wind turbine is located.

Abstract: System and methods are described for real-time biometric monitoring and alert generation. A system may receive biometric data from a mobile device associated with a patient, and may identify a rule defined by a clinician. The system may generate alert data corresponding to a portion of the biometric data in response to determining that the portion of the biometric data satisfies the rule, and the alert data may be transmitted to a device associated with the clinician.

Abstract: The invention relates to a device for transferring heat and a method of controlling such a device, the device comprising a stator chamber containing: a liquid; an input heat exchange surface; an output heat exchanger; and a rotor arranged to be rotated by vapour bubbles.

Abstract: A method of accommodating more than one compute input is provided. The method creates an APD arbitration policy that dynamically assigns compute instructions from a sequence of instructions awaiting processing to the APD compute units for execution of a run list.

Abstract: Provided is a system including a command processor configured for interrupting processing of a first set of instructions executing within a shader core.

Abstract: An airfoil of varying span-wise thickness comprising a suction side and a pressure side coupled together at a leading edge and a trailing edge, with the trailing edge comprising a plurality of spaced-apart wave-shaped projections. Exemplary embodiments provide airfoil geometry and/or trailing edge features to influence downstream wake flow. Methods of fabricating an airfoil for improved wake flow are also provided.

Abstract: A modular multi-turbine unit of fixed toroidal support structures having a rail system designed to allow each of the plurality of turbines to rotate to a most efficient position relative to the wind for generating power, a computer control system capable of positioning each of the plurality of turbines to most effectively generate power from the wind, preventing damage to the turbines, and providing a wind predictive model based on the wind characteristics for the area in which the wind turbine is located.

Abstract: A pulsed fiber laser including fiber preamplifier and power amplifier stages is disclosed. A fiber preamplifier includes first and second preamplifier stages that receive and amplify a seed pulse. A filter isolator placed between the preamplifier stages suppresses noise from the first preamplifier stage. An acoustic optical modulator located in the second preamplifier stage eliminates unwanted wavelengths from the amplified seed pulse received from the first preamplifier stage. The pulsed fiber laser is rugged and lightweight.

Abstract: A modular multi-turbine unit of fixed toroidal support structures having a rail system designed to allow each of the plurality of turbines to rotate to a most efficient position relative to the wind for generating power, a computer control system capable of positioning each of the plurality of turbines to most effectively generate power from the wind, preventing damage to the turbines, and providing a wind predictive model based on the wind characteristics for the area in which the wind turbine is located.

Abstract: A high power integrated fiber laser system includes cascaded amplifiers that utilize low numerical aperture fiber amplifiers. The system is rugged and lightweight.

Abstract: Embodiments described herein provide a method including receiving a command to schedule a first process and selecting a command queue associated with the first process. The method also includes scheduling the first process to run on an accelerated processing device and preempting a second process running on the accelerated processing device to allow the first process to run on the accelerated processing device.

Abstract: The invention is a compression method having characteristics of smooth compression and internal cooling of the gas. Embodiments of the invention employ a cylindrical chamber and an orbiting rotor to create a moving duct or chamber whose walls converge, relative to a static gas packet drawn into the moving duct, at a “pinch point”. Preferably the closing speed of the walls is subsonic and the speed of the pinch point is supersonic. This enables high pressure to co-exist, at the narrowing end of the duct, with low pressure elsewhere in the duct, because of the pressure information barrier produced by the supersonic advance of the pinch point. The invention also discloses means for providing gas inlet and outlet functionality, and means for providing a variable flow compressor.

Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.

Abstract: A method of fabricating an airfoil is provided. The method includes fabricating at least one airfoil including a suction side and a pressure side coupled together at a leading edge and a trailing edge, wherein the airfoil includes a plurality of first and second chord sections each extending between the trailing and leading edges, wherein at least one of the first chord sections extends outward from the pressure side of the airfoil at the trailing edge, and at least one of the second chord sections extends outward from the suction side of the airfoil at the trailing edge.

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.

Abstract: An airfoil of varying span-wise thickness comprising a suction side and a pressure side coupled together at a leading edge and a trailing edge, with the trailing edge comprising a plurality of spaced-apart wave-shaped projections. Exemplary embodiments provide airfoil geometry and/or trailing edge features to influence downstream wake flow. Methods of fabricating an airfoil for improved wake flow are also provided.

Abstract: A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device.

Abstract: A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

Abstract: A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.

Abstract: A memory controller performs a mirror copy function in a way that allows processor accesses to memory to continue during the mirror copy operations that make up the mirror copy function. Data integrity of mirror copy operations is assured by protocols set up in the memory controller. The result is a memory controller that performs a mirror copy function in a way that allows normal processor accesses to memory to be interleaved with mirror copy operations, thereby minimizing the impact on system performance of executing the mirror copy function.