Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: A high power integrated fiber laser system includes cascaded amplifiers that utilize low numerical aperture fiber amplifiers. The system is rugged and lightweight.

Abstract: A high power integrated fiber laser system includes cascaded amplifiers that utilize low numerical aperture fiber amplifiers. The system is rugged and lightweight.

Abstract: A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: A method of fabricating an airfoil is provided. The method includes fabricating at least one airfoil including a suction side and a pressure side coupled together at a leading edge and a trailing edge, wherein the airfoil includes a plurality of first and second chord sections each extending between the trailing and leading edges, wherein at least one of the first chord sections extends outward from the pressure side of the airfoil at the trailing edge, and at least one of the second chord sections extends outward from the suction side of the airfoil at the trailing edge.

Abstract: A modular multi-turbine unit of fixed toroidal support structures having a rail system designed to allow each of the plurality of turbines to rotate to a most efficient position relative to the wind for generating power, a computer control system capable of positioning each of the plurality of turbines to most effectively generate power from the wind, preventing damage to the turbines, and providing a wind predictive model based on the wind characteristics for the area in which the wind turbine is located.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method and computer-readable medium for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.

Abstract: An apparatus and method is disclosed for flushing a cache in a computing system. In a multinode computing system a cache in a first node may contain modified data in an address space of a second node. The cache in the first node must be purged prior to shutting down the first node. The computing system uses a random class replacement scheme for the cache. A cache flush routine sets a cache flush mode in a class replace select mechanism, overriding the random class replacement scheme. With the random class replacement scheme overridden, a minimum number of fetches will flush all the cache lines in the cache, each fetch loading the cache with a cache line not already in the cache. No additional delay penalty is incurred in a critical path through which fetches and stores to the cache must pass.

Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.

Abstract: A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.

Abstract: A computer system includes a computer system having a system memory and a bridging device coupled to the system memory, the bridging device including a memory controller. The computer system also includes a graphics processor unit (GPU) coupled to one port of the bridging device and a central processing unit (CPU) coupled to another port of the bridging device. The GPU and the CPU access the system memory via the memory controller.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: In a data processing system having a memory control device including at least two mirrored memory ports, a method, system, and article of manufacture for processing read requests are disclosed herein. In accordance with the method of the present invention, a read request is received on a system interconnect coupling read requestors with memory resources. The received read request is issued only to a specified one of the at least two mirrored memory ports within the memory control device. In response to detecting an unrecoverable error resulting from the read request issued to the one mirrored memory port, the received read request is issued to an alternate of the at least two mirrored memory ports.

Abstract: A method of generating in-quadrature signals is disclosed. The method comprises phase shifting a Doppler frequency-shifted signal; phase shifting a local oscillator signal; mixing the phase shifted Doppler frequency-shifted signal and the phase-shifted local oscillator signal generating thereby a signal which includes the phase-shifted Doppler frequency-shifted signal and a further phase-shifted local oscillator signal; and mixing the unphase-shifted Doppler frequency-shifted signal and the unphase-shifted local oscillator signal generating thereby a signal which includes the unphase-shifted local oscillator signal and a further phase-shifted Doppler frequency-shifted signal. A method of determining the velocity of an object is also disclosed.

Abstract: A memory controller includes scrub circuitry that performs scrub cycles in a way that does not delay processor reads to memory during the scrub cycle. Atomicity of the scrub operation is assured by protocols set up in the memory controller, not by using an explicit atomic read-correct-write operation. The result is a memory controller that efficiently scrubs memory while minimizing the impact of scrub cycles on system performance.

Abstract: An apparatus and method utilizes system memory as backing stores so that local graphics memory may be oversubscribed. Surfaces may be paged in and out of system memory based on the amount of usage of the surfaces. The apparatus and method also prioritizes surfaces among different tiers of local memory (e.g. frame buffer), non-local memory (e.g. page locked system memory), and system memory backing stores (e.g. pageable system memory) locations based on predefined criteria and runtime statistics relating to the surfaces. As such, local memory may be, for example, expanded without extra memory costs such as adding a frame buffer memory to allow graphics applications to effectively use more memory and run faster.

Abstract: A high power integrated fiber laser system includes cascaded amplifiers that utilize low numerical aperture fiber amplifiers. The system is rugged and lightweight.