Patents by Inventor Philip A. Thomas
Philip A. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210051116Abstract: A method during a first cycle includes receiving, at a first port of a device, a plurality of network packets. The method may include storing, by the device, at least some portion of a first packet of the plurality of network packets at a first address within a first record bank and storing, by the device and concurrent with storing the at least some portion of the first packet from the first address, at least some portion of a second packet of the plurality of network packets at a second address within a second record bank, different than the first record bank. The method may further include storing, by the device, the first address within the first record bank and the second address within the second record bank in the first link stash associated with the first record bank and updating, by the device, a tail pointer to reference the second address.Type: ApplicationFiled: August 14, 2020Publication date: February 18, 2021Inventors: Paul Kim, Philip A. Thomas
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Patent number: 10862513Abstract: A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a parallel decoding of codewords within input data stream based on a codeword type and position.Type: GrantFiled: January 16, 2019Date of Patent: December 8, 2020Assignee: Fungible, Inc.Inventors: Philip A. Thomas, Edward David Beckman, Rajan Goyal, Satyanarayana Lakshmipathi Billa
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Publication number: 20200314026Abstract: A network system for a data center is described in which an access node sprays a data flow of packets over a logical tunnel to another access node. In one example, a method comprises establishing, by a plurality of access nodes, a logical tunnel over a plurality of data paths across a switch fabric between a source access node and a destination access node included within the plurality of access nodes, wherein the source access node is coupled to a source network device; and spraying, by the source access node, a data flow of packets over the logical tunnel to the destination access node, wherein the source access node receives the data flow of packets from the source network device, and wherein spraying the data flow of packets includes directing each of the packets within the data flow to a least loaded data path.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Inventors: Pradeep Sindhu, Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Wael Noureddine, Philip A. Thomas, Satish D Deo, Sunil Mekad, Ayaskant Pani
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Publication number: 20200228148Abstract: A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a parallel decoding of codewords within input data stream based on a codeword type and position.Type: ApplicationFiled: January 16, 2019Publication date: July 16, 2020Inventors: Philip A. Thomas, Edward David Beckman, Rajan Goyal, Satyanarayana Lakshmipathi Billa
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Publication number: 20200169513Abstract: A fabric control protocol is described for use within a data center in which a switch fabric provides full mesh interconnectivity such that any of the servers may communicate packet data for a given packet flow to any other of the servers using any of a number of parallel data paths within the data center switch fabric. The fabric control protocol enables spraying of individual packets for a given packet flow across some or all of the multiple parallel data paths in the data center switch fabric and, optionally, reordering of the packets for delivery to the destination. The fabric control protocol may provide end-to-end bandwidth scaling and flow fairness within a single tunnel based on endpoint-controlled requests and grants for flows. In some examples, the fabric control protocol packet structure is carried over an underlying protocol, such as the User Datagram Protocol (UDP).Type: ApplicationFiled: January 28, 2020Publication date: May 28, 2020Inventors: Deepak Goel, Narendra Jayawant Gathoo, Philip A. Thomas, Srihari Raju Vegesna, Pradeep Sindhu, Wael Noureddine, Robert William Bowdidge, Ayaskant Pani, Gopesh Goyal
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Patent number: 10547333Abstract: In some embodiments, an apparatus includes an optical transceiver which includes a rate-adaptive forward error correction (FEC) encoder and a rate-adaptive FEC decoder. The rate-adaptive FEC encoder is configured to adjust a number of a set of known symbols associated with a codeword to achieve rate adaption. A length of the codeword is fixed. The rate-adaptive FEC encoder is configured to generate the codeword based on (1) a set of information symbols including the set of known symbols and a set of data symbols, and (2) a fixed number of a set of parity symbols generated using information symbols. The rate-adaptive FEC decoder is configured to receive a set of reliability values associated with a channel word, and expand the set of reliability values to produce an expanded set of reliability values. The rate-adaptive FEC decoder is further configured to decode the expanded set of reliability values.Type: GrantFiled: February 26, 2018Date of Patent: January 28, 2020Assignee: Juniper Networks, Inc.Inventors: Murat Arabaci, Marianna Pepe, Philip A. Thomas, David Ofelt, Massimiliano Salsi
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Publication number: 20190379553Abstract: This disclosure describes techniques for providing early acknowledgments to a source device performing a data write operation within a data center or across a geographically-distributed data center. In one example, this disclosure describes a method that includes receiving, by a gateway device and from a source device within a local data center, data to be stored at a remote destination device that is located within a remote data center; storing, by the gateway device, the data to high-speed memory included within the gateway device; transmitting, by the gateway device, the data over a connection to the remote data center; after transmitting the data and before the data is stored at the remote destination device, outputting, by the gateway device to the source device, a local acknowledgment, wherein the local acknowledgment indicates to the source device that the data can be assumed to have been stored at the remote destination device.Type: ApplicationFiled: June 7, 2019Publication date: December 12, 2019Inventors: Pradeep Sindhu, Jaspal Kohli, Philip A. Thomas
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Patent number: 10097479Abstract: In some embodiments, an apparatus comprises a schedule module within a switch fabric system. At a first time, the schedule module is configured to access a list of status indicators associated with a group of egress port indicators. The list of status indicators includes a set of status indicators each of which has a value greater than a threshold. The schedule module is configured to randomly select a status indicator from the set of status indicators and configured to reduce the value of the selected status indicator. The schedule module is then configured to send the egress port indicator associated with the selected status indicator such that a data cell is sent from an egress port associated with that egress port indicator. At a second time, when the value of every status indicator from the list of status indicators is not greater than the threshold, the schedule module is configured to increase the value of every status indicator above the threshold.Type: GrantFiled: March 31, 2016Date of Patent: October 9, 2018Assignee: Juniper Networks, Inc.Inventors: Philip A. Thomas, Sarin Thomas, Jean-Marc Frailong, Pradeep Sindhu
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Patent number: 9906243Abstract: In some embodiments, an apparatus includes an optical transceiver which includes a rate-adaptive forward error correction (FEC) encoder and a rate-adaptive FEC decoder. The rate-adaptive FEC encoder is configured to adjust a number of a set of known symbols associated with a codeword to achieve rate adaption. A length of the codeword is fixed. The rate-adaptive FEC encoder is configured to generate the codeword based on (1) a set of information symbols including the set of known symbols and a set of data symbols, and (2) a fixed number of a set of parity symbols generated using information symbols. The rate-adaptive FEC decoder is configured to receive a set of reliability values associated with a channel word, and expand the set of reliability values to produce an expanded set of reliability values. The rate-adaptive FEC decoder is further configured to decode the expanded set of reliability values.Type: GrantFiled: March 24, 2016Date of Patent: February 27, 2018Assignee: Juniper Networks, Inc.Inventors: Murat Arabaci, Marianna Pepe, Philip A. Thomas, David Ofelt, Massimiliano Salsi
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Patent number: 9838138Abstract: Techniques are described for determining pre-compensation parameters to compensate for signal integrity degradation along a signal path. A processor generates a first digital signal and receives a second digital signal. The second digital signal is generated from an optical-to-electrical conversion of a feedback optical signal that is generated from an electrical-to-optical conversion of an electrical signal by an optical module. The processor determines the pre-compensation parameters based on the first and second digital signals.Type: GrantFiled: December 30, 2015Date of Patent: December 5, 2017Assignee: Juniper Networks, Inc.Inventors: Murat Arabaci, Marianna Pepe, Massimiliano Salsi, Philip A. Thomas, David James Ofelt
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Patent number: 9331929Abstract: At a first time, a schedule module is configured to access a list of status indicators associated with a group of egress port indicators. The list of status indicators includes a set of status indicators each of which has a value greater than a threshold. The schedule module is configured to randomly select a status indicator from the set of status indicators and configured to reduce the value of the selected status indicator. The schedule module is then configured to send the egress port indicator associated with the selected status indicator such that a data cell is sent from an egress port associated with that egress port indicator. At a second time, when the value of every status indicator from the list of status indicators is not greater than the threshold, the schedule module is configured to increase the value of every status indicator above the threshold.Type: GrantFiled: March 29, 2012Date of Patent: May 3, 2016Assignee: Juniper Networks, Inc.Inventors: Philip A. Thomas, Sarin Thomas, Jean-Marc Frailong, Pradeep Sindhu
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Patent number: 9258192Abstract: A multi-chassis network device may automatically detect whether cables connected between chassis devices are correctly inserted. The device may insert, into a first data stream output from a first port of the device, control information identifying the first port. The device may receive, from a second data stream received by the first port of the device, second control information identifying a second port, at another device connected to the device via a cable. The device may determine, based on the second control information, whether the connection of the first port to the second port, via the cable, is valid and cause, when the connection of the first port to the second port is determined to not be valid, the device to output an indication that the connection is not valid or to reconfigure the device to make the connection of the first port to the second port valid.Type: GrantFiled: January 3, 2014Date of Patent: February 9, 2016Assignee: Juniper Networks, Inc.Inventors: Philip A. Thomas, Anurag Agrawal
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Patent number: 9240843Abstract: In some embodiments, an apparatus includes a coherent optical receiver that can receive during a first time period a set of in-phase signals and a set of quadrature signals having a skew from the set of in-phase signals. The coherent receiver can blindly determine a delay between the set of in-phase signals and the set of quadrature signals based on the set of in-phase signals and the set of quadrature signals. The delay includes an intersymbol portion and an intrasymbol portion. The coherent optical receiver can apply the delay at a second time after the first time period such that a skew after the second time is less than the skew at the first time period.Type: GrantFiled: December 28, 2012Date of Patent: January 19, 2016Assignee: Juniper Networks, Inc.Inventors: Christian Malouin, Philip A. Thomas, Murat Arabaci, Bo Zhang, Theodore J. Schmidt, Roberto Marcoccia
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Patent number: 9225431Abstract: This disclosure describes the Fast Chromatic Dispersion Estimation (FCDE) techniques which corrects for chromatic dispersion in high data rate optical communications systems such as some coherent optical communications systems. FCDE may utilize transform such as fast-Fourier transforms to estimate the chromatic dispersion. From an estimate of the chromatic dispersion, the techniques may determine filter tap coefficients for compensating the chromatic dispersion.Type: GrantFiled: March 29, 2013Date of Patent: December 29, 2015Assignee: Juniper Networks, Inc.Inventors: Murat Arabaci, Christian Malouin, Philip A. Thomas, Theodore John Schmidt, Roberto Marcoccia
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Patent number: 9104345Abstract: First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues.Type: GrantFiled: March 14, 2014Date of Patent: August 11, 2015Assignee: Juniper Networks, Inc.Inventors: Anurag Agrawal, Philip A. Thomas
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Patent number: 9077466Abstract: In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.Type: GrantFiled: December 3, 2012Date of Patent: July 7, 2015Assignee: Juniper Networks, Inc.Inventors: Sarin Thomas, Srihari Vegesna, Pradeep Sindhu, Chi-Chung Kenny Chen, Jean-Marc Frailong, David J. Ofelt, Philip A. Thomas, Chang-Hong Wu
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Patent number: 9021582Abstract: This disclosure describes techniques of determining whether a symbol stream includes a pattern defined by a regular expression. As described herein, the regular expression may be represented using a non-deterministic finite automaton (NFA). A plurality of states in the NFA may be evaluated in parallel. These states may be associated with a plurality of symbol positions in a symbol stream. Evaluating a plurality of states and symbols in parallel may allow for faster determinations of whether the symbol stream includes the pattern defined by the regular expression.Type: GrantFiled: April 24, 2007Date of Patent: April 28, 2015Assignee: Juniper Networks, Inc.Inventors: Gary Goldman, Philip A. Thomas, Ramesh Panwar
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Patent number: 8953951Abstract: This disclosure describes the Fast Chromatic Dispersion Estimation (FCDE) techniques which corrects for chromatic dispersion in high data rate optical communications systems such as some coherent optical communications systems. FCDE may utilize transform such as fast-Fourier transforms to estimate the chromatic dispersion. From an estimation of the chromatic dispersion, the techniques may determine filter tap coefficients for compensating the chromatic dispersion.Type: GrantFiled: June 19, 2012Date of Patent: February 10, 2015Assignee: Juniper Networks, Inc.Inventors: Philip A. Thomas, Christian Malouin, Theodore John Schmidt
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Patent number: 8804711Abstract: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.Type: GrantFiled: December 29, 2008Date of Patent: August 12, 2014Assignee: Juniper Networks, Inc.Inventors: Gunes Aybay, Jaya Bandyopadhyay, Jean-Marc Frailong, Pradeep Sindhu, Philip A. Thomas, Anjan Venkatramani
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Patent number: 8804710Abstract: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.Type: GrantFiled: December 29, 2008Date of Patent: August 12, 2014Assignee: Juniper Networks, Inc.Inventors: Gunes Aybay, Jaya Bandyopadhyay, Jean-Marc Frailong, Pradeep Sindhu, Philip A. Thomas, Anjan Venkatramani