Patents by Inventor Philip Damberg
Philip Damberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110285020Abstract: A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts.Type: ApplicationFiled: August 2, 2011Publication date: November 24, 2011Applicant: TESSERA RESEARCH LLCInventors: Belgacem Haba, Philip Damberg, Philip R. Osborn
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Patent number: 8008785Abstract: A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts.Type: GrantFiled: June 4, 2010Date of Patent: August 30, 2011Assignee: Tessera Research LLCInventors: Belgacem Haba, Philip Damberg, Philip R. Osborn
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Publication number: 20110147928Abstract: Microelectronic assemblies can have multiple conductive bond elements, e.g., bond wires, or a lead bond and a bond wire, extending between a pair of a substrate contact and a chip contact. E.g., a first bond wire can have ends joined to the contacts of the chip and substrate. A second bond wire can be joined to the ends of the first bond wire so that the second bond wire does not touch either the chip contact or the substrate contact to which the first bond wire is joined. In one example, a bond wire has a looped connection with first and second ends joined at a first contact and a middle portion joined to a second contact. In one example, first and second bond elements, e.g., bond wires or lead bonds can connect first and second pairs of a substrate contact with a chip contact. A third bond element, e.g., a bond wire or bond ribbon, can be joined to ends of the first and second bond elements.Type: ApplicationFiled: December 22, 2009Publication date: June 23, 2011Applicant: TESSERA RESEARCH LLCInventors: Belgacem Haba, Philip Damberg, Philip R. Osborn
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Publication number: 20110147953Abstract: A microelectronic assembly includes a semiconductor chip having chip contacts exposed at a first face and a substrate juxtaposed with a face of the chip. A conductive bond element can electrically connect a first chip contact with a first substrate contact of the substrate, and a second conductive bond element can electrically connect the first chip contact with a second substrate contact. The first bond element can have a first end metallurgically joined to the first chip contact and a second end metallurgically joined to the first substrate contact. A first end of the second bond element can be metallurgically joined to the first bond element. The second bond element may or may not touch the first chip contact or the substrate contact. A third bond element can be joined to ends of first and second bond elements which are joined to substrate contacts or to chip contacts.Type: ApplicationFiled: June 4, 2010Publication date: June 23, 2011Applicant: TESSERA RESEARCH LLCInventors: Belgacem Haba, Philip Damberg, Philip R. Osborn
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Publication number: 20100193970Abstract: A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.Type: ApplicationFiled: April 13, 2010Publication date: August 5, 2010Applicant: TESSERA, INC.Inventors: Philip Damberg, Belgacem Haba, David B. Tuckerman, Teck-Gyu Kang
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Patent number: 7732912Abstract: A microelectronic element package has one or more individual carrier units overlying a region or regions of the front or rear surface of the microelectronic element, leaving other regions of the microelectronic element surface uncovered. The carrier units can be made economically using only a small area of a dielectric film or other circuit panel material.Type: GrantFiled: August 11, 2006Date of Patent: June 8, 2010Assignee: Tessera, Inc.Inventor: Philip Damberg
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Patent number: 7709968Abstract: A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.Type: GrantFiled: November 10, 2004Date of Patent: May 4, 2010Assignee: Tessera, Inc.Inventors: Philip Damberg, Belgacem Haba, David B. Tuckerman, Teck-Gyu Kang
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Patent number: 7521785Abstract: A semiconductor assembly includes plural chips stacked one above the other. One or more of the chips is a magnetic random access memory (MRAM). Use of MRAM alleviates problems caused by heat dissipation in the stack.Type: GrantFiled: December 21, 2004Date of Patent: April 21, 2009Assignee: Tessera, Inc.Inventors: Philip Damberg, Nicholas J. Colella
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Publication number: 20090071707Abstract: A method is provided for manufacturing a multilayer substrate. An insulating layer can have a hole overlying a patterned second metal layer. In turn, the second metal layer can overlie a first metal layer. A third metal layer can be electroplated onto the patterned second metal layer within the hole, the third metal layer extending from the second metal layer onto a wall of the hole. When plating the third metal layer, the first and second metal layers can function as a conductive commoning element.Type: ApplicationFiled: August 13, 2008Publication date: March 19, 2009Applicant: Tessera, Inc.Inventors: Kimitaka Endo, Philip Damberg, Craig S. Mitchell, Sean Moran, Christopher Wade, Belgacem Haba, John Riley
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Publication number: 20080277775Abstract: A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals.Type: ApplicationFiled: May 11, 2007Publication date: November 13, 2008Applicant: Tessera, Inc.Inventors: Kenneth Allen Honer, Philip Damberg
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Publication number: 20080036060Abstract: A microelectronic element package has one or more individual carrier units overlying a region or regions of the front or rear surface of the microelectronic element, leaving other regions of the microelectronic element surface uncovered. The carrier units can be made economically using only a small area of a dielectric film or other circuit panel material.Type: ApplicationFiled: August 11, 2006Publication date: February 14, 2008Applicant: Tessera, Inc.Inventor: Philip Damberg
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Publication number: 20070166876Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.Type: ApplicationFiled: January 3, 2006Publication date: July 19, 2007Applicant: Tessera, Inc.Inventors: Young-Gon Kim, David Gibson, Michael Warner, Philip Damberg, Philip Osborn
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Patent number: 7149095Abstract: A stacked microelectronic assembly includes a plurality of microelectronic subassemblies. Each subassembly includes a substrate having at least one site, a plurality of first contacts and a plurality of second contacts. Each subassembly also has at least one microelectronic element assembled to the at least one attachment site and electrically connected to at least some of the first and second contacts. The substrate is folded so that the first contacts are accessible at a bottom of a subassembly and the second contacts are accessible at a top of a subassembly. The plurality of subassemblies are stacked one on top of another in a generally vertical configuration. The substrate of at least one of the subassemblies has a plurality of attachment sites and a plurality of microelectronic elements assembled to the attachment sites. The substrate is folded so that at least some of the plurality of microelectronic elements are disposed alongside one another.Type: GrantFiled: October 28, 2002Date of Patent: December 12, 2006Assignee: Tessera, Inc.Inventors: Michael Warner, Philip Damberg, John B. Riley, David Gibson, Young-Gon Kim, Belgacem Haba, Vernon Solberg
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Patent number: 7061122Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.Type: GrantFiled: October 10, 2003Date of Patent: June 13, 2006Assignee: Tessera, Inc.Inventors: Young-Gon Kim, David Gibson, Michael Warner, Philip Damberg, Philip Osborn
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Publication number: 20050184399Abstract: A semiconductor assembly includes plural chips stacked one above the other. One or more of the chips is a magnetic random access memory (MRAM). Use of MRAM alleviates problems caused by heat dissipation in the stack.Type: ApplicationFiled: December 21, 2004Publication date: August 25, 2005Applicant: Tessera, Inc.Inventors: Philip Damberg, Nicholas Colella
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Publication number: 20050173805Abstract: A microelectronic package includes a microelectronic element having faces and contacts, a flexible substrate overlying and spaced from a first face of the microelectronic element, and a plurality of conductive terminals exposed at a surface of the flexible substrate. The conductive terminals are electrically interconnected with the microelectronic element and the flexible substrate includes a gap extending at least partially around at least one of the conductive terminals. In certain embodiments, the package includes a support layer, such as a compliant layer, disposed between the first face of the microelectronic element and the flexible substrate. In other embodiments, the support layer includes at least one opening that is at least partially aligned with one of the conductive terminals.Type: ApplicationFiled: November 10, 2004Publication date: August 11, 2005Applicant: Tessera, Inc.Inventors: Philip Damberg, Belgacem Haba, David Tuckerman, Teck-Gyu Kang
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Publication number: 20050167817Abstract: The present invention is directed to a circuit panel assembly. The assembly includes a circuit panel having a top surface and a first microelectronic element mounted on the circuit panel. The first microelectronic element includes a bottom surface overlying the top surface of the circuit panel and defining a gap therebetween. The assembly further may include an array of electrical contacts exposed on the bottom surface of the first microelectronic element. The contacts include a first set connected to the circuit panel and a second set. The assembly also includes an adaptor having a substrate including a first region and an additional region. The substrate has oppositely directed inner and outer surfaces in the first region. The adaptor further having a plurality of connection pads exposed at the inner surface in the first region. The adaptor preferably includes at least one functional element in the additional region electrically connected to at least some of the connection pads.Type: ApplicationFiled: January 19, 2005Publication date: August 4, 2005Applicant: Tessera, Inc.Inventor: Philip Damberg
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Patent number: 6885106Abstract: A stacked microelectronic assembly includes a dielectric element and a first and second microelectronic element stacked one atop the other with the first microelectronic element disposed between the second microelectronic element and the dielectric. The dielectric element has opposed first and second surfaces with conductive features exposed at the first surface and terminals exposed on the second surface. Preferably, the contact-bearing face of the first microelectronic element confronts the first surface of the dielectric with at least some of the conductive features being movable with respect to the contacts or terminals. By providing such movable features, joining units have heights of about 300 microns or less may be joined to the terminals thereby reducing the overall height of the microelectronic assembly to 1.2 mm and less.Type: GrantFiled: January 11, 2002Date of Patent: April 26, 2005Assignee: Tessera, Inc.Inventors: Philip Damberg, Craig S. Mitchell, John B. Riley, Michael Warner, Joseph Fjelstad
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Publication number: 20040262777Abstract: An ultra thin system-in-a-package (SIP) with independent test and repair capability comprises an interposer having arranged on a top surface and a bottom surface thereof a number of packaged semiconductor chips mounted via solder bumps in accordance with a Land Grid Array (LGA) format and wherein no underfill is used on the SIP.Type: ApplicationFiled: October 10, 2003Publication date: December 30, 2004Applicant: Tessera, Inc.Inventors: Young-Gon Kim, David Gibson, Michael Warner, Philip Damberg, Philip Osborn
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Publication number: 20040245617Abstract: A memory chip module includes multiple stacks of memory chips arranged on a base panel. The chip stacks desirably are arranged in rows symmetrical about a central plane and define a channel in a central region of the base panel. Control chips such as a register chip associated with the memory chips in the stacks can be provided in this central region of the base panel. Desirably, the base panel is surface-mountable on a circuit board. The module provides high memory chip packing density, effective cooling and short, balanced signal lines between the control chip and the memory chip stacks.Type: ApplicationFiled: May 5, 2004Publication date: December 9, 2004Applicant: Tessera, Inc.Inventors: Philip Damberg, Ilyas Mohammed