Abstract: A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.

Abstract: A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates.

Abstract: An apparatus includes a receiver, an error detection unit, and an acknowledgement unit. The receiver may receive frames of data from a transmitter unit of a second apparatus via a first communication path. The error detection unit may detect data errors in the frames of data received via the first communication path. The acknowledgment unit may maintain an acknowledgement indicator indicative of whether frames received by the apparatus are error free. In response to the error detection unit detecting an error, the acknowledgement unit may indicate an error condition exists by freezing a value of the acknowledgement indicator, or alternatively the acknowledgement unit may set a current value of the acknowledgement indicator to a predetermined error value. Further, the apparatus may successively convey values of the acknowledgement indicator to the second apparatus via a second communication path while the apparatus is receiving frames.

Abstract: A packet-based traffic switching system with error detection and correction without taking the system offline. The system tests offline paths without interfering with other online paths. Also, the system tests online paths even while no data cell traffic is sent over the paths. The system responds to the addition or removal of paths or path components without interrupting cell traffic. The system detects and selectively flushes defective paths without impacting paths that are working properly. The system initializes new switching fabrics automatically without using software to set values. Thus, the system tests online paths and corrects errors without going offline.

Abstract: A traffic forwarding system that uses a multicast start-of-packet (SOP) pointer to enqueue a multicast packet in packet queues. The system receives cells, assigns pointers to the cells, and stores the received cells in memory. The system assigns multicast SOP pointers to multicast SOP cells. The system reassembles cells into packets and enqueues the packets in packet queues for forwarding. A multicast packet is enqueued in a plurality of packet queues. The memory in which the multicast packet is stored is released after the multicast packet is dequeued from each of the plurality of packet queues.

Abstract: A traffic control system and method with flow control aggregation. The system includes a switching fabric and an ingress module. The switching fabric includes read counters that are associated with a plurality of queues. The read counters represent an aggregated number of cells dequeued from respective queues since a previous flow control message (FCM) was sent to the ingress module. The read counters are reset when a FCM is created. The ingress module includes write counters that are associated with the queues. The write counters are incremented each time a cell is sent to the respective queues. The write counters are decremented in accordance with the FCM when the FCM is received. Also, read counters for one or more queues are aggregated into a single FCM.

Abstract: A system for efficiently reassembling packets from cells received on independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by skipping the fabrics in striping and reassembly sequences. When fabrics are added, the fabrics are included in the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

Abstract: Multi-stage arbitration at a switching fabric. The switching fabric includes a traffic profiler that generates a request for a cell with a specified traffic class. The switching fabric includes a first stage arbitration between traffic classes of cells enqueued at the switching fabric that modifies the request. The switching fabric further includes a second stage arbitration between cells enqueued at the switching fabric that uses the modified request.

Abstract: A system for efficiently sending cells in-order to independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by deleting the fabrics from striping and reassembly sequences. When fabrics are added, the fabrics are added to the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single-ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.

Abstract: A packet-based traffic switching system with error detection and correction without taking the system offline. The system tests offline paths without interfering with other online paths. Also, the system tests online paths even while no data cell traffic is sent over the paths. The system responds to the addition or removal of paths or path components without interrupting cell traffic. The system detects and selectively flushes defective paths without impacting paths that are working properly. The system initializes new switching fabrics automatically without using software to set values. Thus, the system tests online paths and corrects errors without going offline.

Abstract: A traffic forwarding system that uses a multicast start-of-packet (SOP) pointer to enqueue a multicast packet in packet queues. The system receives cells, assigns pointers to the cells, and stores the received cells in memory. The system assigns multicast SOP pointers to multicast SOP cells. The system reassembles cells into packets and enqueues the packets in packet queues for forwarding. A multicast packet is enqueued in a plurality of packet queues. The memory in which the multicast packet is stored is released after the multicast packet is dequeued from each of the plurality of packet queues.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single- ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.

Abstract: A system for efficiently reassembling packets from cells received on independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by skipping the fabrics in striping and reassembly sequences. When fabrics are added, the fabrics are included in the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

Abstract: A traffic control system and method with flow control aggregation. The system includes a switching fabric and an ingress module. The switching fabric includes read counters that are associated with a plurality of queues. The read counters represent an aggregated number of cells dequeued from respective queues since a previous flow control message (FCM) was sent to the ingress module. The read counters are reset when a FCM is created. The ingress module includes write counters that are associated with the queues. The write counters are incremented each time a cell is sent to the respective queues. The write counters are decremented in accordance with the FCM when the FCM is received. Also, read counters for one or more queues are aggregated into a single FCM.

Abstract: Multi-stage arbitration at a switching fabric. The switching fabric includes a traffic profiler that generates a request for a cell with a specified traffic class. The switching fabric includes a first stage arbitration between traffic classes of cells enqueued at the switching fabric that modifies the request. The switching fabric further includes a second stage arbitration between cells enqueued at the switching fabric that uses the modified request.

Abstract: A system for efficiently sending cells in-order to independent switching fabrics according to a serial high speed interface (HSI) protocol. The system includes redundancy in that fabrics may be removed by deleting the fabrics from striping and reassembly sequences. When fabrics are added, the fabrics are added to the striping and reassembly sequences. The system is efficient due in part to in-order transmission of cells serially across multiple fabrics. Full fabric bandwidth is thereby utilized without reordering overhead. Since packets are striped across all available fabrics, load is balanced across the fabrics.

Abstract: Certain bits in existing op code formats for a processor do not change from one instruction to another when particular classes of instructions are used. Applicants optionally utilize one or more of these bits to identify one of a plurality of different register files from which to retrieve operands or to store the results of an operation. These bits along with allocated address bits in predetermined address fields now allow the processor to address many more registers. This can be used to increase the performance of the processor. Those programs not utilizing the bits outside of the address fields for designating a particular register file are backwards compatible with the modified processor.