Abstract: Embodiments of the invention include method, systems and computer program products for servicing indirect storage requests. Method includes decoding a storage request instruction and sending to a first one of a plurality of memory controllers an address represented by a first pointer associated with at least a portion of the storage request instruction. A first memory is used to read information associated with a second pointer contained at the address. The first memory forwards the storage request instruction to a second one of the plurality of memory controllers, wherein the second one of the plurality of memory controllers is associated with and/or manages a memory location represented by the second pointer. The second one of the plurality of memory controllers reads and forwards data associated with the storage request instruction to a processor using the second pointer. The processor writes the forwarded data in a destination register of the processor.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.

Abstract: Embodiments include method, systems and computer program products for fusing one or more transaction request messages. The computer-implemented method includes comparing, using a memory controller, at least two electronic transaction request messages and determining if the at least two electronic transaction request messages are of a same electronic transaction request message type. The memory controller is used to determine that the at least two electronic transaction request messages are directed to associated portions of memory based at least in part on determining that the at least two electronic transaction request messages are the same electronic transaction request message type. The memory controller fuses the at least two electronic transaction request messages based at least in part on determining that the at least two electronic transaction request messages are directed to associated portions of memory.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: A computer-implemented method includes receiving, at a memory controller, a new transaction request referencing a new transaction to be executed on a memory. The memory includes two or more memory groups embodying two or more memory technologies, and the memory controller includes two or more group request queues with a respective group request queue corresponding to each memory group of the two or more memory groups. A memory group is selected, by the memory controller, from among the two or more memory groups. The transaction request is placed, by the memory controller, on the respective group request queue corresponding to the selected memory group. The new transaction is executed on the selected memory group. A new response to the new transaction is received, by the memory controller, from the selected memory group. The new response is returned.

Abstract: Embodiments include method, systems and computer program products for fusing one or more transaction request messages. The computer-implemented method includes comparing, using a memory controller, at least two electronic transaction request messages and determining if the at least two electronic transaction request messages are of a same electronic transaction request message type. The memory controller is used to determine that the at least two electronic transaction request messages are directed to associated portions of memory based at least in part on determining that the at least two electronic transaction request messages are the same electronic transaction request message type. The memory controller fuses the at least two electronic transaction request messages based at least in part on determining that the at least two electronic transaction request messages are directed to associated portions of memory.

Abstract: Embodiments of the invention include method, systems and computer program products for servicing indirect storage requests. Method includes decoding a storage request instruction and sending to a first one of a plurality of memory controllers an address represented by a first pointer associated with at least a portion of the storage request instruction. A first memory is used to read information associated with a second pointer contained at the address. The first memory forwards the storage request instruction to a second one of the plurality of memory controllers, wherein the second one of the plurality of memory controllers is associated with and/or manages a memory location represented by the second pointer. The second one of the plurality of memory controllers reads and forwards data associated with the storage request instruction to a processor using the second pointer. The processor writes the forwarded data in a destination register of the processor.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: A method for branch prediction, the method comprising, receiving a branch wrong guess instruction having a branch wrong guess instruction address and data including an opcode and a branch target address, determining whether the branch wrong guess instruction was predicted by a branch prediction mechanism, sending the branch wrong guess instruction to an execution unit responsive to determining that the branch wrong guess instruction was predicted by the branch prediction mechanism, and receiving and decoding instructions at the branch target address.

Abstract: Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present disclosure, an integrated wafer-level processing system includes a memory wafer and a processing element connected to the memory wafer via a data connection.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.

Abstract: Methods and systems for managing memory and stress to memory systems. A method for managing memory includes receiving from a software application memory retention requirements for application data. The memory retention requirements include storage duration length and/or criticality of data retention. The method also includes storing the application data in one of a plurality of memory regions in non-volatile memory based on the memory retention requirements and memory retention characteristics of the memory regions. Each memory region may have different memory retention characteristics.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: An aspect includes receiving a request to access data in a memory, the request from a requesting processor and including a virtual address of the data. It is determined, based on contents of a page table that a plurality of physical addresses in the memory corresponds to the virtual address. The physical addresses include a first physical address of a primary memory location in a first partition accessed via a bus that is communicatively coupled to a port of a first processor, and a second physical address of a secondary memory location in a second partition accessed via a bus that is communicatively coupled to a port of a second processor. Contents of the primary memory location in the first partition were previously copied into the secondary memory location. Based on the requesting processor, one of the physical addresses is selected and data at the selected physical address is accessed.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.

Abstract: A computer-implemented method includes receiving first data representing a first physical object that has three dimensions. The first data may be stored, by a computer processor, as a first digital object representing the first physical object. Storing the first data may include storing a representation of the first data in a first plurality of layers. Each layer of the first plurality of layers may include a first plurality of cells. Each cell of the first plurality of cells may have one of: a first value indicating that the first physical object exists in a physical space corresponding to a position of the cell, and a second value indicating that the first physical object does not exist in the physical space corresponding to the position of the cell.